Constrain a type RECORD in VHDL, error!!!!!

[bacbac]

Hi, I have a problem when trying to work with complex number in VHDL.
I declare type of RECORD to simulate a complex number without constraint, then I try to constrain it when I using after.
Here is my code:

---

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
 
entity fft2 is
port(   x1: in  std_logic;
        x2: in  std_logic;
        x3: out std_logic_vector(3 downto 0));
end entity;
 
architecture fft2_arch of fft2 is
 
   type COMPLEX is
        record
                RE: signed ;
                IM: signed;
        end record;
    signal x     :COMPLEX(RE(2 downto 0),IM(2 downto 0));
    signal y     :COMPLEX(RE(1 downto 0),IM(1 downto 0));
 
begin
end fft2_arch;

---

The error is:
" Error (10410): VHDL Type Conversion error at fft2.vhd(19): Type Conversion near text or symbol "COMPLEX" must have one argument "

Did I constrain the type of RECORD wrong?
:???::???::???:

 

[TrickyDicky]

in VHDL pre-2008, you have to constrain a record type when you declare it, so you have to do something like this:

type complex is
  record
    re: signed(7 downto 0);
    im : signed(7 downto 0);
  end record;

But in VHDL 2008 you can do what you want. Make sure you use the -2008 compile switch in modelsim or whatever compiler you're using.

 

[bacbac]

in VHDL pre-2008, you have to constrain a record type when you declare it, so you have to do something like this:

type complex is
  record
    re: signed(7 downto 0);
    im : signed(7 downto 0);
  end record;

But in VHDL 2008 you can do what you want. Make sure you use the -2008 compile switch in modelsim or whatever compiler you're using.

Thanks TrickyDicky!
In the program Quartus II, I have chosen Setting/Analysis and synthesis settings/ VHDL input/ VHDL 2008 and OK,
It took no change and the error is still exist.
Any suggestion?

 

[TrickyDicky]

unfortunatly Quartus (and ISE for that matter) are a bit poor when it comes to VHDL 2008 support (even modelsim was a bit lax until more recent edditions).
Raise an enhancement request, and they may get round to it one day.

 

[bacbac]

unfortunatly Quartus (and ISE for that matter) are a bit poor when it comes to VHDL 2008 support (even modelsim was a bit lax until more recent edditions).
Raise an enhancement request, and they may get round to it one day.

Thanks TrickyDicky,