bacbac
Newbie level 5
Hi, I have a problem when trying to work with complex number in VHDL.
I declare type of RECORD to simulate a complex number without constraint, then I try to constrain it when I using after.
Here is my code:
The error is:
" Error (10410): VHDL Type Conversion error at fft2.vhd(19): Type Conversion near text or symbol "COMPLEX" must have one argument "
Did I constrain the type of RECORD wrong?
:???::???::???:
I declare type of RECORD to simulate a complex number without constraint, then I try to constrain it when I using after.
Here is my code:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_signed.all; entity fft2 is port( x1: in std_logic; x2: in std_logic; x3: out std_logic_vector(3 downto 0)); end entity; architecture fft2_arch of fft2 is type COMPLEX is record RE: signed ; IM: signed; end record; signal x :COMPLEX(RE(2 downto 0),IM(2 downto 0)); signal y :COMPLEX(RE(1 downto 0),IM(1 downto 0)); begin end fft2_arch;
The error is:
" Error (10410): VHDL Type Conversion error at fft2.vhd(19): Type Conversion near text or symbol "COMPLEX" must have one argument "
Did I constrain the type of RECORD wrong?
:???::???::???: