Constant input to an entity

[shaiko]

Suppose we have a VHDL component called "some_component" with an input port called "some_input" that drives a large block of combinatorial logic.
What will happen to "some_component" if we drive "some_input" with a constant value when we instantiate it?

1."some_component" will still be synthesized fully.
2.The output of "some_component" will also become a constant.

 

[std_match]

The "constant logic" will be optimized away at some optimization stage.
This is not always true in the ASIC world when a large design is divided into subchips. A constant input to a subchip will not be optimized.
I think that similar things also can happen in the FPGA world if a region is "locked" to save time on synthesis, place and route.

 

[shaiko]

So,

If it isn't "locked" with an appropriate attribute it'll simply optimize away - always ?

 

[mrflibble]

If a constant input results in a constant output, AND the synthesizer is able to detect this , THEN yes it will optimize it away AFAIK. If you want to prevent this you'll have to use constraints like "KEEP" and "SAVE".

 

[TrickyDicky]

If it isn't "locked" with an appropriate attribute it'll simply optimize away - always ?

Why wouldnt it? The logic does nothing.