connecting vga to rom then display a simple bitmap

[andreahmed]

I have generated a VGA signal, and succeeded to draw a rectangle. I have also code for ROM designed using VHDL, and initialized with a file that has patterns. I'm beginner in VHDL and FPGA. I would like to read the contents of the ROM and use the VGA generator to display the contents.

here are the codes.

LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 ------------------------------------------------------------------
 ENTITY rom IS
 PORT (address: IN INTEGER RANGE 0 TO 15;
 data_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
 END rom;
 ------------------------------------------------------------------
 ARCHITECTURE rom OF rom IS
 SIGNAL reg_address: INTEGER RANGE 0 TO 15;
 TYPE memory IS ARRAY (0 TO 15) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
 SIGNAL myrom: memory;
 ATTRIBUTE ram_init_file: STRING;
 ATTRIBUTE ram_init_file OF myrom: SIGNAL IS "test.coe";
 BEGIN
 data_out <= myrom(address);
 END rom;

VGA Generator Code

architecture Behavioral of VGA_display is   
    -- Intermediate register telling the exact position on display on screen.
    signal x : integer range 0 to 1023 := 100;
    signal y : integer range 0 to 1023 := 80;
    signal addr: INTEGER RANGE 0 TO 15;
    signal pix: STD_LOGIC_VECTOR(7 DOWNTO 0);
begin
 -- On every positive edge of the clock counter condition is checked,
  output1: process(clock)
  begin

	  rom1: entity rom port map(address => addr, data_out => pix);

    if rising_edge (clock) then
        -- If the counter satisfy the condition, then output the colour that should appear.
        if (hcounter >= 1)  and (hcounter < 120) and (vcounter >= 1) and (vcounter < 120
                   ) then
        addr <= vcounter * 128 + hcounter;
	pixels <= pix;
                 
        -- If the condition is not satisfied then the output colour will be black.
        else 
          pixels <= x"00";
        end if;
      end if;
   end process;
end Behavioral;

 

[TrickyDicky]

And whats the problem?

 

[andreahmed]

The ROM is not initalized. I tried to make a test bench, but the data is always undefined.
That's the first problem.

The second problem, is I tried to use constant data in the ROM, and I get bars, not bitmaps picture.

 

[ads-ee]

COE file? Isn't this ram_init_file attribute supposed to be used with a MIF file?

See if this thread helps you out.

 

[andreahmed]

Thanks,

Now I have a problem of reading the bitmap into the VGA. What I get is a vertical bars. Not that bitmapped data.

 

[ads-ee]

Thanks,

Now I have a problem of reading the bitmap into the VGA. What I get is a vertical bars. Not that bitmapped data.

This seems to suggest you've never run a simulation of the design (maybe due to your original COE file initialization problem). With a simulation you could easily determine why the data is showing up as vertical bars.

I suggest you get the simulation running correctly with the MIF file initialization then look at how the data is being sent to the VGA. (change some of the VGA pattern data to make sure you know where/when the pixels are being sent).

 

[andreahmed]

i have made a simple test bench for ROM. I would like to write a test bench for a VGA display. I'm kinda beginner so I don't know how to write it. I know I need to generate a clock, but how would I generate the counters,..etc. Thanks so much! here is my vhdl design

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity VGA_display is
          port (
            -- Assuming 50MHz clock.If the clock is reduced then it might give the unexpected output.      
                  clock: in std_logic;

             -- The counter tells whether the correct position on the screen is reached where the data is to be displayed. 
                  hcounter: in integer range 0 to 1023;
                  vcounter: in integer range 0 to 1023;

          -- Output the colour that should appear on the screen. 
                  pixels : out std_logic_vector(7 downto 0)               
                );
end VGA_display;

architecture Behavioral of VGA_display is   
    -- Intermediate register telling the exact position on display on screen.
         signal x : integer range 0 to 1023 := 100;
         signal y : integer range 0 to 1023 := 80;
         signal addr: INTEGER RANGE 0 TO 15;
         signal pix: STD_LOGIC_VECTOR(7 DOWNTO 0);
                   -- Clock period definitions
         constant Clk_period : time := 10 ns;

begin


      rom1: entity work.rom port map(address => addr, data_out => pix, clk => clock);



 -- On every positive edge of the clock counter condition is checked,
  output1: process(clock)
              begin
                    if rising_edge (clock) then

                    -- If the counter satisfy the condition, then output the colour that should appear.
                        if (hcounter >= 1)  and (hcounter < 128) and (vcounter >= 1) and (vcounter < 128
                               ) then

                           addr <= vcounter * 128 + hcounter;

                           pixels <= pix; 

                    -- If the condition is not satisfied then the output colour will be black.
                        else 
                          pixels <= x"00";
                        end if;
              end if;
           end process;
end Behavioral;