andreahmed
Newbie level 4
I have generated a VGA signal, and succeeded to draw a rectangle. I have also code for ROM designed using VHDL, and initialized with a file that has patterns. I'm beginner in VHDL and FPGA. I would like to read the contents of the ROM and use the VGA generator to display the contents.
here are the codes.
VGA Generator Code
here are the codes.
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
------------------------------------------------------------------
ENTITY rom IS
PORT (address: IN INTEGER RANGE 0 TO 15;
data_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END rom;
------------------------------------------------------------------
ARCHITECTURE rom OF rom IS
SIGNAL reg_address: INTEGER RANGE 0 TO 15;
TYPE memory IS ARRAY (0 TO 15) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL myrom: memory;
ATTRIBUTE ram_init_file: STRING;
ATTRIBUTE ram_init_file OF myrom: SIGNAL IS "test.coe";
BEGIN
data_out <= myrom(address);
END rom;
Code:
architecture Behavioral of VGA_display is
-- Intermediate register telling the exact position on display on screen.
signal x : integer range 0 to 1023 := 100;
signal y : integer range 0 to 1023 := 80;
signal addr: INTEGER RANGE 0 TO 15;
signal pix: STD_LOGIC_VECTOR(7 DOWNTO 0);
begin
-- On every positive edge of the clock counter condition is checked,
output1: process(clock)
begin
rom1: entity rom port map(address => addr, data_out => pix);
if rising_edge (clock) then
-- If the counter satisfy the condition, then output the colour that should appear.
if (hcounter >= 1) and (hcounter < 120) and (vcounter >= 1) and (vcounter < 120
) then
addr <= vcounter * 128 + hcounter;
pixels <= pix;
-- If the condition is not satisfied then the output colour will be black.
else
pixels <= x"00";
end if;
end if;
end process;
end Behavioral;