Connecting substrate to two different potentials in CMOS

[jbord39]

Hey all,

I am working on an analog to digital converter. The basic problem I am encountering is that in one portion of my circuit I need to operate on 0-3.3V (digital part) and in another portion (analog part) I need to operate on -3.3V to 3.3V.

Since the NMOS substrates are all tied together, I cannot do this directly.

I am assuming this is a common problem in CMOS so I figured I would ask if anyone could give me some suggestions.

My ideas to solve this problem are:
1. Use guard rings to isolate the NMOS substrates in my digital part from my analog part. My question here is what guard rings should I use (p-guard ring or N-guard ring) and what potential should I connect to the guard ring (0V or -3.3V...??).


Any help is appreciated,

John

 

[Teddy]

a) what is your substrate (wafer) P or N. If P then your NMOS is probably not in separate NWELL and so guardring will not help.
b) draw a crossection and look for all the diodes in the structure - that will show you that guardring is not good.
c) best solution would be to keep all digital or analog NMOS devices in deep Nwell (or if you have trench even better). Possibly you could have some burried layer in your analog part and put all analog to separate island.

 

[jbord39]

The substrate is P-type.

p-type analog (-3.3V) ||| n+ guard ring (+3.3V) ||| p-type digital (0V)
-3.3V --->|----- 3.3V -------|<----- 0V

It seems like even if the analog p-sub is connected to 0V and the digital p-type sub is connected to 0V that still they would be electrically isolated.

What am I missing?

-Thanks,

John

-EDIT:

Thinking about it I guess the P-type substrates would still be connected together underneath the n+ guard ring. So how do you make these islands you are talking about?