Connecting Multiply FPGAs together

[AB27]

How to connect multiply FPGAs together by common data bus? What signal standard should I shoose?

Number of FPGAs 10
Bus frequency 100 MHz
Bus width 64 bit

Supported signal standards:
Single-Ended GTL, HSTL, LVCMOS, LVTTL, SSTL.
Differential LVDS, LDT, LVPECL, RSDS.

 

[farhada]

It all depends on what you want to do.

Do you want to create a 74 bit data bus? Or is it a piplelined structure when you want to use multiple FPGAs doing data processing.

BR,
/Farhad

 

[Al Farouk]

if you have a processor that drive this data bus then configure the FPGA to comply with the same standard the processor use. but if your circuit consists only from FPGA then refer to the data sheets which descrip each standard and choose to configure all of them to the standard that give you all system requirements.

 

[AB27]

I need 64 bit data bus + some control signals such as chip select, read/write, interrupt pins etc. One FPGA acts as a Master, the others - Slaves. The Master initiates data transfer with one of the Slaves.

I reviewed data sheets. It's easy to connect 2 devices but it's still unclear how to connect multiply devices. The problem is - signal integrity. What signal standard should I use? How to terminate the bus? Should I split the bus into small segments?

 

[andy1]

From an analog point of view, although I am new to FPGA but have some experience in high speed, having a 64 bit bus running at 100MHz is not easy. Imagine all of the 64 bit making a transition from 0 to 1 or 1 to 0 at the same time. The cross talk and ground bounce is just incredible at those transition. You mention that there are 10 devices which means physically the bus has to be pretty long so reflection will be a problem. Also the speed of the clock will be determine by how long the bus physically and the longer the bus, the harder to run a fast clock.

Make sure you have good ground and power.

Would you consider having a switch in stead of a shared bus? Similar to PCI Express architecture which will surely improve speed. Though logic design is a little harder with a switch but easier electrically and physically. Maybe there is a off the shell switch you can use but I really don't know.

 

[blueagate]

I think choose the SSTL is better, many high speed devices such as DDR SDRM using SSTL standard.
Using differential signal standard means double number wires have to be deal with in PCB design, adding difficulty.

 

[Al Farouk]

you need to get a look in one of the Text books (Available on the forum) talk about high speed PCB design to get information that guid you during design.

 

[Black Jack]

I think that LVDS is right choice
Use SERDES`s (SERializer DESerilizer) and you have LVDS link`s for 64 bit 66 MHz bus (4 link x 16Bit x 66 MHz, for example) and change bus topology to star topology.
You can develop custom internal SERDES in FPGA, or use ready chips,
e.g. from National (**broken link removed**)

 

[speedoak]

I need 64 bit data bus + some control signals such as chip select, read/write, interrupt pins etc. One FPGA acts as a Master, the others - Slaves. The Master initiates data transfer with one of the Slaves.

I reviewed data sheets. It's easy to connect 2 devices but it's still unclear how to connect multiply devices. The problem is - signal integrity. What signal standard should I use? How to terminate the bus? Should I split the bus into small segments?

no problem to connect multiple FPGA together by using a BUS, just like a PCI bus.
here the working speed is important, what is the bus working frequency??
if 33Mhz like PCI bus speed, it is no problem to connect upto 8 devices, but pay attention to layout.
if 66Mhz, three or four devices should be no problem, but need careful alyout and routing.