Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

SFP and Xilinx FPGAs

mtnkh

Newbie
Joined
Mar 1, 2021
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
27
Hi,

Actually I used a "10 Gigabit Ethernet Subsystem v3.1 IP core" and kintex7/Ultrascale FPGAs to run SFP and it would seem that everything runs ok. But I have a problem. Whenever connect a SFP cable between two FPGA-based boards they send and receive data without any error but when I connect the SFP cable between PC (it has sfp pcie card) and one of the FPGA-based board some of the received packets by the PC will be lost. What is the problem?. what is the difference between PC and FPGA-based board?

Thanks
 

dpaul

Advanced Member level 4
Joined
Jan 16, 2008
Messages
1,465
Helped
306
Reputation
612
Reaction score
301
Trophy points
1,373
Location
Germany
Activity points
10,977
What is the problem?. what is the difference between PC and FPGA-based board?
You have the data and test/setup, you tell us what is the difference!
Maybe then the problem can be guessed.

Else you have to build a test setup for debugging>
1. FPGA1 to FPGA2 : Have a frame generator and checker built inside your design implemented with FPGA1. Have a frame loopback mechanism inside your design in FPGA2. Make a test such that all frames sent out from FPGA1 are loopbacked from FPAG2 and verified in FPGA1 as they are received. Test this in hardware. e.g. even if 1 loopbacked frame has error then light up an on-board LED or something like that.
2. FPGA to PC - You can use Wireshark to monitor the received frames.

That's the best I can help you for the info you have provided.
 

mtnkh

Newbie
Joined
Mar 1, 2021
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
27
What is the problem?. what is the difference between PC and FPGA-based board?
You have the data and test/setup, you tell us what is the difference!
Maybe then the problem can be guessed.

Else you have to build a test setup for debugging>
1. FPGA1 to FPGA2 : Have a frame generator and checker built inside your design implemented with FPGA1. Have a frame loopback mechanism inside your design in FPGA2. Make a test such that all frames sent out from FPGA1 are loopbacked from FPAG2 and verified in FPGA1 as they are received. Test this in hardware. e.g. even if 1 loopbacked frame has error then light up an on-board LED or something like that.
2. FPGA to PC - You can use Wireshark to monitor the received frames.

That's the best I can help you for the info you have provided.
Thanks for your reply, I send UDP packets (data is a counter, it means each byte is one greater than the previous one) to FPGA2 by FPGA1 and in FPGA2, I subtract the new byte from the old one and in a case the value is not 1 it shows an error so the error-counter will be increase by one and I see the result by VIO in Vivado. This system is be used in computer too. I mean I have a software which subtract the new byte from the old one and in a case is not equal to 1 the error-counter increases. When I send UDP packets from FPGA1 to FPGA2 there is not any error I mean the Error-Counter is zero but in PC by my software it increases rapidly. I also tracked the packets by Wireshark and I saw some packets have been lost! I don't know it is the problem of sfp pcie card or not I mean its buffer is small or the GTH transceivers function of FPGA work better with FPGAs and I should change GTH configuration! I have no idea!
 

dpaul

Advanced Member level 4
Joined
Jan 16, 2008
Messages
1,465
Helped
306
Reputation
612
Reaction score
301
Trophy points
1,373
Location
Germany
Activity points
10,977
It is difficult to debug in hardware. But I assume you have a simulation model of your design and have run it successfully and observed expected behavior before board level implementation.

You can do something like this...
Put an ILA core at the i/f of MAC1 and PHY1 (FPGA1 or sending board) and have Wireshark running at your PC. Send the packets one-by-one, observe them in the ILA and after receipt, observe them in Wireshark.

I don't know it is the problem of sfp pcie card or not I mean its buffer is small or the GTH transceivers function of FPGA work better with FPGAs and I should change GTH configuration! I have no idea!

Then make sure that the PC Ethernet settings have been configured as per the Eth data rate used for packet exchange.
 

barry

Advanced Member level 5
Joined
Mar 31, 2005
Messages
5,075
Helped
1,108
Reputation
2,228
Reaction score
1,099
Trophy points
1,393
Location
California, USA
Activity points
27,813
My guess would be that the PC is busy doing other things besides handling your ethernet, whereas the FPGA boards don't have the burden of the operating system getting in the way.
 

niciki

Full Member level 2
Joined
Apr 11, 2018
Messages
139
Helped
31
Reputation
62
Reaction score
33
Trophy points
38
Location
Gdańsk, Poland
Activity points
957
For problems with MGTs (Multi-Gigabit Transceivers), I suggest to use Integrated Bit Error Ratio Tester (IBERT) at each side.
Check IBERT IP core:
Ultrascale: https://www.xilinx.com/products/intellectual-property/ibert_ultrascale_gth.html
Kintex-7: https://www.xilinx.com/products/intellectual-property/chipscope_ibert_7series_gtx.html

It gives you the possibility to find the best configuration for the link (measuring the opened eye) and gives you BER out of the box without ILA/VIO.
Ideally would be to have IBERT equivalent at PC side also.
 

dpaul

Advanced Member level 4
Joined
Jan 16, 2008
Messages
1,465
Helped
306
Reputation
612
Reaction score
301
Trophy points
1,373
Location
Germany
Activity points
10,977
For problems with MGTs (Multi-Gigabit Transceivers), I suggest to use Integrated Bit Error Ratio Tester (IBERT) at each side.
@niciki , the OP must 1st determine where the frames are getting broken or lost. That will determine where the debugging should begin.
 

niciki

Full Member level 2
Joined
Apr 11, 2018
Messages
139
Helped
31
Reputation
62
Reaction score
33
Trophy points
38
Location
Gdańsk, Poland
Activity points
957
the OP must 1st determine where the frames are getting broken or lost. That will determine where the debugging should begin.
MGT alone has so many variables around that can have not optimal values for actual connection and IBERT gives control over all variables regarding transceivers, so it is always a good starting point. Things like clock sources, pin assignments, different loopbacks can be checked.
The rest like cabels/fibers quality/dirt on fibers/routes quality on PCB are to be checked at further steps and also with using IBERT.

I suggest to use IBERT at FPGA side and make near and far loopbacks inside SFP at PC side. Then use sweep tests in which you can select the ranges for transceiver TX/RX attributes and port values to get optimal values for actual connection. Then use the same values in your "10 Gigabit Ethernet Subsystem v3.1 IP core".
 

LaTeX Commands Quick-Menu:

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top