I want to connect Virtex-5 Fpga to TMS320C6474 DSP via RapidIO,SRIO and
AIF . Can you guide me.
I think that in schematic onle a CAP 0.1F seri is sufficient. Is it true?
How can I design the schematic?
RapidIO in Virtex-5 has several standards.
The physical interface is not particular difficult, but you will need to purchase the Xilinx SRIO IP-Core and implement that, etc.
A number of companies have already done that and it might be more cost-effective to contract such experts. We haev NOT connected to a 'C6474, but to other TI DSPs