module Ui_UPDATION_CALCULATOR(si,clk,rst,cs,ui_new);
input [63:0] si;
output reg [63:0] ui_new;
input clk,rst,cs;
parameter ct=64'b0011111110111001100110011001100110011001100110011001100110011010;//ct=.1
parameter u_initial=64'b0100000000100100000000000000000000000000000000000000000000000000;//10.0
parameter si_min=64'b0100000000011111110001011111000001101111011010010100010001100111;//7.9433
reg ce1,ce2,ce3;
reg [63:0] u_last;
wire [63:0] u_temp;
wire [63:0] z1,z2;
always @(*) begin
if (cs)begin
if (rst) begin
u_last=u_initial;
end
else begin
ce1=1'b1;
ce2=1'b1;
ce3=1'b1;
u_last=u_temp;
end
ce1=1'b1;
ce2=1'b1;
ce3=1'b1;
ui_new=u_temp;
end else
begin
ce1=1'b0;
ce2=1'b0;
ce3=1'b0;
u_last=u_temp;
ui_new=u_last;
end
end
SUBTRACTOR_CORE s1(
.a(si), // Bus [63 : 0]
.b(si_min), // Bus [63 : 0]
.operation_rfd(),
.clk(clk),
.ce(ce1),
.result(z1)); // Bus [63 : 0]
MULTIPLIER_CORE m1(
.a(z1), // Bus [63 : 0]
.b(ct), // Bus [63 : 0]
.operation_rfd(),
.clk(clk),
.ce(ce2),
.result(z2)); // Bus [63 : 0]
SUBTRACTOR_CORE s2(
.a(u_last), // Bus [63 : 0]
.b(z2), // Bus [63 : 0]
.operation_rfd(),
.clk(clk),
.ce(ce3),
.result(u_temp)); // Bus [63 : 0]
endmodule