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confusion in disabling a signal in verilog!!

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Indrajit Ghosh

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i have written a verilog code , and a part of the code looks like this....



Code Verilog - [expand]
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always @(*) begin
 
if (cs)begin
 
if (rst) begin
 
u_last=u_initial;
 
end
else begin
ce1=1'b1;
ce2=1'b1;
ce3=1'b1;
u_last=u_temp; 
end
 
ce1=1'b1;
ce2=1'b1;
ce3=1'b1;
 
ui_new=u_temp;
end else
begin
 
ce1=1'b0;
ce2=1'b0;
ce3=1'b0;
u_last=u_temp;
ui_new=u_last;
end
 
end



now what i want to do is that i want to disable the 'rst' signal whenever the if statement i.e " if(rst) " is executed,the rst signal is a net type....where to put the disabling statement?
 
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sharath666

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Within an always block you can set/reset only reg datatype and not nets/wires. You will have to define a reg datatype for rst and disable it.
 

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I actually don't think this code will work as the OP expects.

for instance the following lines:

Code Verilog - [expand]
1
2
u_last=u_temp;
ui_new=u_last;



both u_last and ui_new are going to be the same as u_temp when the always block finishes. Basically this just ends up making a wire connection between u_temp and ui_new.

I think the OP should draw a schematic of the design, they need to understand that the code represents a digital circuit.

I've also never seen a chipselect (cs?) that has priority over the reset (rst?). In this design you have to select the device to reset it? I'm not certain, but this looks like you'll end up with a latch for u_last and possibly for ui_new.

Well you don't get a latch but you end up with a pretty meaningless result...
Capture.JPG
This is the schematic after RTL elaboration.

If you force u_last to exist, then you get this result
Capture.JPG
Not much of an improvement if you ask me.
 

Indrajit Ghosh

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actually this is a part of the code....here some parts like u_temp is a net type variable coming out from the output of a core which can be only net type,and to assign it to a register i used that type of mechanism.... perhaps i may be wrong since i am new in verilog but atleast it works...:smile:
 

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at least it works...:smile:
what in simulation? It certainly doesn't work as a register synthesis wise.

You state you are new at Verilog, so accept the fact that you are writing really bad code and look at the templates for a FF on sites like http://asic-world.com/index.html. The current code isn't assigning anything to a "register". What you've written isn't a register and the RTL parser I used shows it's not.
 

Indrajit Ghosh

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Code:
module Ui_UPDATION_CALCULATOR(si,clk,rst,cs,ui_new);


input [63:0] si;
output reg [63:0] ui_new;
input clk,rst,cs;
parameter ct=64'b0011111110111001100110011001100110011001100110011001100110011010;//ct=.1
parameter u_initial=64'b0100000000100100000000000000000000000000000000000000000000000000;//10.0
parameter si_min=64'b0100000000011111110001011111000001101111011010010100010001100111;//7.9433
reg ce1,ce2,ce3;
reg [63:0] u_last;
wire [63:0] u_temp;
wire [63:0] z1,z2;


always @(*) begin

if (cs)begin

if (rst) begin

u_last=u_initial;

end
else begin

ce1=1'b1;
ce2=1'b1;
ce3=1'b1;
u_last=u_temp; 
end

ce1=1'b1;
ce2=1'b1;
ce3=1'b1;

ui_new=u_temp;
end else
begin

ce1=1'b0;
ce2=1'b0;
ce3=1'b0;
u_last=u_temp;
ui_new=u_last;
end

end


SUBTRACTOR_CORE s1(
	.a(si), // Bus [63 : 0] 
	.b(si_min), // Bus [63 : 0] 
	.operation_rfd(),
	.clk(clk),
	.ce(ce1),
	.result(z1)); // Bus [63 : 0] 


MULTIPLIER_CORE m1(
	.a(z1), // Bus [63 : 0] 
	.b(ct), // Bus [63 : 0] 
	.operation_rfd(),
	.clk(clk),
	.ce(ce2),
	.result(z2)); // Bus [63 : 0] 


SUBTRACTOR_CORE  s2(
	.a(u_last), // Bus [63 : 0] 
	.b(z2), // Bus [63 : 0] 
	.operation_rfd(),
	.clk(clk),
	.ce(ce3),
	.result(u_temp)); // Bus [63 : 0] 

endmodule

this is the full code,maybe not a well written code (since i am new in verilog)....but can someone give me some tips on how to remove this rst signal ,what i want to achieve is that the starting value of ui_last should be u_initial and then afterwards it is u_temp. (cs =control signal)
 

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You can't store anything with a combinational always block, and if you do code something that stores a value it's going to have a feedback path and will implement a latch. Latches are not good in an FPGA as they are implemented using LUTs.

If you need to store something you should be using a FF with an enable.

Do you know the difference between the coding of combinatorial logic and edge triggered (FF) logic? Review the Verilog tutorial at ASIC-world. They also have an examples area.
 

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how to know whether the code forms a latch or not? since the synthesizer is not showing any warnings nor any error!
 

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Because if you look at the elaborated RTL schematic I posted in #3 there are no combinational loops in your code. Ergo no warnings about latches.
 

sharath666

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The synthesizer will show you a warning about a latch being inferred.
 

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