confused by this logic circuit

[abcyin]

confused by this circuit

Hi, all

anybody tell me, that do you have experience on the attached circuit? it's interesting that the input data and clock will go to DATA and CLK terminals of the group of DFFs crossly, and the simulation results are really confusing, so anybody give me some hints on that?

thanks in advance!

 

[Prototyp_V1.0]

One step (hopefully in right direction): Redraw the schematic in this way:
1: Change the wires from the AND gate to all flipflops Q output.
2: Make it a inverted OR gate.

Personally I think it's way more difficult to dela with extra inverted outputs. This way the circuit will do the same.

Where did you get that circuit from? For me it looks like the bit order must follow a rule to get the output to change. But I have no clue what to use this for. Maybe to check some phase, but that's just wild guess.

interresting circuit by the way. Mee too wonder if it can be applied to some application.

 

[erikl]

Re: confused by this circuit

... so anybody give me some hints on that?

I guess this circuit checks for a possible setUp or hold time violation, and with its output result it is possible to invalidate the data received via an extra FF.

 

[DigitalLogician]

It seems best to view this circuit as Asynchronous sequential. The incoming clock signal seems to be just a convenient signal generator. Also, other than for delaying purposes or strength boosting, two inverters would just be as good as the four used.

This circuit makes creative use of the D-latches. So ignore that the clk inputs are labeled clk -- they are just data inputs (label them B if you want). See these data latches if that helps **broken link removed**.

Also a review of multiplexers may help a little since they signals seem muxed at the end **broken link removed**.

Good luck

 

[abcyin]

One step (hopefully in right direction): Redraw the schematic in this way:
1: Change the wires from the AND gate to all flipflops Q output.
2: Make it a inverted OR gate.

Personally I think it's way more difficult to dela with extra inverted outputs. This way the circuit will do the same.

Where did you get that circuit from? For me it looks like the bit order must follow a rule to get the output to change. But I have no clue what to use this for. Maybe to check some phase, but that's just wild guess.

interresting circuit by the way. Mee too wonder if it can be applied to some application.

I have to say sorry, that it seems that it makes no sense if I just change the connections or change the AND gate to OR gate, the simulation always give me a "0" or a "1" , because two of the DFFs give a constant value due to the crossed connection of input data and clock, which is the key issue I am really confusing about.

Added after 3 hours 46 minutes:

Also a review of multiplexers may help a little since they signals seem muxed at the end **broken link removed**.

Good luck

But the end of the circuit is not a four-to-one mux, it's just an AND gate.
meanwhile, could you explain why do you think it is an asynchronous sequential circuit?

 

[erikl]

... the simulation always give me a "0" or a "1" , because two of the DFFs give a constant value due to the crossed connection of input data and clock, which is the key issue I am really confusing about.

Did you try a simulation of data & clock signal edges which would generate setUp or hold time violations? I.e. with data to clock edge (or clock to data edge) time differences of < 100ps ?

 

[venky4u]

i think the circuit should give "0" as output in normal conditions..
and it will give "1" as output when any violations occur.
the functionality of the circuit is

(clk'.data').(clk.data).(clk.data').(clk'data)

this functionality gives output as for any given input,
but when there is any violation and data is not captured properly..
which may result in 1 as output..

this is what i understood..
correct me if iam wrong...