[SOLVED] Conformal Tool in FPGA Full CHip design

[nohj_yar]

HI All! Im a beginner in this forum and currently studying as a MS student. Im studying Cadence COnformal tool to check the equivalence of RTL to gate-level netlist. Now I've done the latter. My question is that is there any possible way to check the formal equivalence of a gate-level netlist or (RTL netlist) versus FULL CHip FPGA netlist?

 

[sharath666]

Nobody uses conformal for FPGA designs. It is used only for ASIC designs. Why would you want to do that anyways? Just get the design on a FPGA and start validating it...

 

[ads-ee]

FULL CHip FPGA netlist?

What is this supposed to mean? FPGA netlists are either EDIF or RTL like any other netlist. If you mean the proprietary (i.e. the secret format) vendor post map, post place and route netlist, then definitely there is no way to do any kind of formal verification.

Nobody uses conformal for FPGA designs. It is used only for ASIC designs. Why would you want to do that anyways? Just get the design on a FPGA and start validating it...

Well you might want to use it to check synthesis results given that the synthesis tools provided by FPGA vendors sometimes have had bugs.

In practical terms you wouldn't use a formal verification tool on an FPGA design not because it doesn't add value to your process, but because typical budgets for engineering to produce FPGA designs is typically not the same kind of budget for doing ASIC design. When you can start doing FPGA designs with a budget for a PC of $1200 (i7 quad core, 16GB memory), a tools budget of $3000 (Vivado, includes a simulator, or free if you are using a Webpack supported device!), and a Xilinx Platform cable USB for $225, that doesn't even start to make a dent in the price of one seat of Cadence Conformal or any other ASIC development tool.

Besides that if your FPGA doesn't work there less chance that you'll sink the entire companies future when you have to download a new FPGA bit file to fix the problem.

 

[nohj_yar]

Nobody uses conformal for FPGA designs. It is used only for ASIC designs. Why would you want to do that anyways? Just get the design on a FPGA and start validating it...

The existing verification in FPGA designs as i have read in the papers consumes a long time. NOw im thinking if i will used formal verification in a full chip FPGA versus gate-level netlist, maybe it will result to shorter verification time, this is my main reason.

What do you mean nobody? Is there no one even cared to do this idea?

 

[sharath666]

As ads-ee has mentioned, there are budget constraints for every project. Moreover conformal runs for RTL vs post synthesis netlists hardly yield any failures. There is nothing as good as actually testing your code on hardware.

 

[ads-ee]

The existing verification in FPGA designs as i have read in the papers consumes a long time. NOw im thinking if i will used formal verification in a full chip FPGA versus gate-level netlist, maybe it will result to shorter verification time, this is my main reason.

I really think that the reason that FPGA verification is taking so long isn't so much the lack of formal verification is the lack of a formal processes for development and verification of the design in the first place. Too many FPGA designs are done in a more or less ad hoc fashion as the engineer doing the design doesn't have tools, management support, ASIC training, FPGA training, etc. I've seem more than my fair share of FPGA "designs" (I use that term loosely) that looked more like D (1.0 on a 4.0 scale) graded student projects. It's obvious if you don't have a process, don't have a clear idea how to write a testbench, don't have a methodology on how and what to verify in simulation what to verify in the lab, that you'll likely end up doing all your verification and debug in the lab, where it will take significantly longer to iron out the problems. Beside with the useless testbench that was originally written you'll be finding numerous system level problems in the lab, since the design never truly had any design verification simulations done on it.

 

[nohj_yar]

I really think that the reason that FPGA verification is taking so long isn't so much the lack of formal verification is the lack of a formal processes for development and verification of the design in the first place. Too many FPGA designs are done in a more or less ad hoc fashion as the engineer doing the design doesn't have tools, management support, ASIC training, FPGA training, etc. I've seem more than my fair share of FPGA "designs" (I use that term loosely) that looked more like D (1.0 on a 4.0 scale) graded student projects. It's obvious if you don't have a process, don't have a clear idea how to write a testbench, don't have a methodology on how and what to verify in simulation what to verify in the lab, that you'll likely end up doing all your verification and debug in the lab, where it will take significantly longer to iron out the problems. Beside with the useless testbench that was originally written you'll be finding numerous system level problems in the lab, since the design never truly had any design verification simulations done on it.

What i mean is that the current fpga designers uses verification through simulation to validate the full-chip fpga. NOw, that method applies a large number of input vectors to the circuit. As designs become larger and more complex, the simulation will take a longer time. Now I'm thinking that I will used formal verification method instead of verification through simulation on full chip fgpa vs gate-level netlist hoping that it will reduce the validation time.

 

[sharath666]

Formal verification is not going to replace your simulations. Formal verification is meant to check whether the structure of the netlist is as per the RTL. IT IS NOT MEANT TO CONFIRM THE FUNCTIONALITY OF THE LOGIC. There is now way of escaping simulations.Once you simulate your RTL, you can then use conformal to check whether the netlist is the same as the RTL so that you proceed with confidence with that netlist.

 

[nohj_yar]

Formal verification is not going to replace your simulations. Formal verification is meant to check whether the structure of the netlist is as per the RTL. IT IS NOT MEANT TO CONFIRM THE FUNCTIONALITY OF THE LOGIC. There is now way of escaping simulations.Once you simulate your RTL, you can then use conformal to check whether the netlist is the same as the RTL so that you proceed with confidence with that netlist.

Yeah you are right @sharath666. I'm not replacing the verification through simulation, i'm just want to prove in my study that formal verification between full chip fpga netlist and gate level netlist is feasible..