I really think that the reason that FPGA verification is taking so long isn't so much the lack of formal verification is the lack of a formal processes for development and verification of the design in the first place. Too many FPGA designs are done in a more or less ad hoc fashion as the engineer doing the design doesn't have tools, management support, ASIC training, FPGA training, etc. I've seem more than my fair share of FPGA "designs" (I use that term loosely) that looked more like D (1.0 on a 4.0 scale) graded student projects. It's obvious if you don't have a process, don't have a clear idea how to write a testbench, don't have a methodology on how and what to verify in simulation what to verify in the lab, that you'll likely end up doing all your verification and debug in the lab, where it will take significantly longer to iron out the problems. Beside with the useless testbench that was originally written you'll be finding numerous system level problems in the lab, since the design never truly had any design verification simulations done on it.