rafimiet
Member level 5
I have to find maximum of a sequence. For that I have written a code below:
When I synthesize it I get the following ERROR:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity threshold_calculator is GENERIC (word_length : INTEGER := 8); Port ( data1,data2 : in STD_LOGIC_VECTOR (word_length-1 downto 0);--input can be negative as well we1,we2 : in STD_LOGIC;-- Consider input for Max calculation or not max_coeff : out STD_LOGIC_VECTOR (word_length-2 downto 0));--- This is the maximum of sequence end threshold_calculator; architecture Behavioral of threshold_calculator is signal s1,s2,s4,s5 : SIGNED (word_length-1 downto 0); signal s3,s6,s7,s8 : SIGNED (word_length-2 downto 0); signal thrsh,thrsh1 : SIGNED (word_length-2 downto 0) := (OTHERS => '0'); begin ---- Get Magnitude of first input data --- s1 <= signed(data1) WHEN we1 = '1' ELSE (OTHERS => '0'); s2 <= -s1; s3 <= s1(word_length-2 downto 0) WHEN data1(word_length-1) = '0' ELSE s2(word_length-2 downto 0); ---- Get Magnitude of second input data --- s4 <= signed(data2) WHEN we2 = '1' ELSE (OTHERS => '0'); s5 <= -s4; s6 <= s4(word_length-2 downto 0) WHEN data2(word_length-1) = '0' ELSE s5(word_length-2 downto 0); --- Compare the two inputs --- s7 <= s3 WHEN s3 > s6 ELSE s6; s8 <= s7; --- Comapare with already maximum yielded --- thrsh <= s7 WHEN s8 > thrsh1 ELSE UNAFFECTED; thrsh1 <= thrsh; max_coeff <= std_logic_vector(thrsh); end Behavioral;
When I synthesize it I get the following ERROR:
It also affects my simulation which is very obvious. Please suggest me how to make it work in concurrent code. Because in sequential code, I know how to suppress it.[Synth 8-327] inferring latch for variable 'thrsh_reg'