libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.NUMERIC_STD.ALL;entity threshold_calculator isGENERIC(word_length :INTEGER:=8);Port( data1,data2 :inSTD_LOGIC_VECTOR(word_length-1downto0);--input can be negative as well
we1,we2 :inSTD_LOGIC;-- Consider input for Max calculation or not
max_coeff :outSTD_LOGIC_VECTOR(word_length-2downto0));--- This is the maximum of sequenceend threshold_calculator;architecture Behavioral of threshold_calculator issignal s1,s2,s4,s5 :SIGNED(word_length-1downto0);signal s3,s6,s7,s8 :SIGNED(word_length-2downto0);signal thrsh,thrsh1 :SIGNED(word_length-2downto0):=(OTHERS=> '0');begin---- Get Magnitude of first input data ---
s1 <=signed(data1)WHEN we1 = '1' ELSE(OTHERS=> '0');
s2 <=-s1;
s3 <= s1(word_length-2downto0)WHEN data1(word_length-1)= '0' ELSE
s2(word_length-2downto0);---- Get Magnitude of second input data ---
s4 <=signed(data2)WHEN we2 = '1' ELSE(OTHERS=> '0');
s5 <=-s4;
s6 <= s4(word_length-2downto0)WHEN data2(word_length-1)= '0' ELSE
s5(word_length-2downto0);--- Compare the two inputs ---
s7 <= s3 WHEN s3 > s6 ELSE
s6;
s8 <= s7;--- Comapare with already maximum yielded ---
thrsh <= s7 WHEN s8 > thrsh1 ELSEUNAFFECTED;
thrsh1 <= thrsh;
max_coeff <=std_logic_vector(thrsh);end Behavioral;
When I synthesize it I get the following ERROR:
[Synth 8-327] inferring latch for variable 'thrsh_reg'
It also affects my simulation which is very obvious. Please suggest me how to make it work in concurrent code. Because in sequential code, I know how to suppress it.
Line 34 and 35 implement a memory function, I presume intentionally. It's not possible without latches or registers.
The message is a synthesis warning, not an error. In the present code it's indicating potentially unsafe behavior. A safe maximum memory can be implemented with clocked registers.
As reported by the warning, the latch is implemented for the conditional assignment to thrsh. Respectively this assignment must performed in an edge sensitive process.
Code C - [expand]
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if rising_edge(clk) then
if s7 > thrsh then
thrsh <= s7;
end if;
end if;
Your original code was a warning, not an error, but using latches are not recommended.
If your code:
Code:
thrsh <= s7 WHEN s8 > thrsh1 ELSE UNAFFECTED;
thrsh can only change when s8 > thrsh1, otherwise it stays at the same value - this requires memory, and hence the latch as no clock is involved.
To avoid latches, either synchronise the circuit (like you did) or ensure every signal is assigned a new value in all cases.