Concept of Negative setup time

[VirtuosoDracula]

Hi,

Can anybody please explain if the setup time could be negative.
If yes, under what conditions?

As per my understanding if setup time is negative, then the data is coming after the active clock edge, thus leading to capture of old data.

Please help to explain this concept.

Thanks in advance
VD!

 

[verylsi]

hi,

The set up time equation is -
Tc2q + Tcomb + Tsetup ≤ Tclk + Tskew

Tsetup ≤ (Tclk + Tskew) - ( Tc2q + Tcomb )

Under the condition when Tc2q + Tcomb > than Tclk + Tskew then Tsetup will be negative.

So mainly your aim is to design such that that the combination logic is minimal, specially when you are using a high frequency clock.

http://www.edn.com/design/analog/4371393/Understanding-the-basics-of-setup-and-hold-time

This link covers in depth analysis of set up and hold time

 

[std_match]

There is nothing strange with a negative setup time. Imagine a delay in the clock line.
If the data and clock switches at the same time. the data will arrive first to the register.
If you delay the clock enough, the setup time will be negative.