COMPOSOR CDL out problem also

[jcpu]

Dear Sir:

when I use CDL out to export netlist from CADENCE composor to HSPICE...
there is a line of "*.PININFO..." like:

.SUBCKT sc_res_P2_2d34P A1 A3 CK<1> CK<2> CK<3> CK<4> CK<5> CK<6> CK<7> CK<8>
+VAG VDD VSS
*.PININFO A1:B A3:B CK<1>:B CK<2>:B CK<3>:B CK<4>:B CK<5>:B CK<6>:B CK<7>:B
+CK<8>:B VAG:B VDD:B VSS:B
MM0 net054 net25 net054 VDD PD W=10u L=10u M=4
MM1 net054 net25 net054 VDD PD W=6.8u L=10u M=1
XI169 A1 net054 CK<7> CK<8> VDD VSS / switch_A
XI159 net25 A3 CK<3> CK<4> VDD VSS / switch_A
XI0 net054 VAG CK<5> CK<6> VDD VSS / switch_A
XI1 net25 VAG CK<1> CK<2> VDD VSS / switch_A
.ENDS

where most of other simulator shall take line "+CK<8>:B VAG:B VDD:B VSS:B" as comtinuation of .SUBCKT definition and syntax error occurs.
Please advise how to avoid this.


Also here is another problem of CDL out often met is:
When we define subcircuit parameter as pPar("LP")...
say in an invertor circuit. It's good for design and simualtion.
But when later we need to export its netlist for LVS or HSPICE postsim.
Netlist obtain from CDL out is:
******************************************************************
* Library Name: logic
* Cell Name: inv
* View Name: schematic
******************************************************************
.SUBCKT inv A VDD VSS Y
*.PININFO A:I Y VDD:B VSS:B
MN0 Y A VSS VSS N W=WN L=LN M=M
MP1 Y A VDD VDD P W=WP L=LP M=M
.ENDS
********************************************************************
===>
which is short of something like "WN=1u LN=0.5u WP=1u LP=0.5u M=1"
in the tail of first line to match the calling sequence

*******************************************************************
.SUBCKT LNA_v2 ENA IN NBIAS OUT VDD VSS
*.PININFO ENA:B IN:B NBIAS:B OUT:B VDD:B VSS:B
XI7 ENA VDD VSS ENAB / inv LP=0.7u WP=2.6u M=1 LN=0.7u WN=1.3u
RR5 OUT VSS 3K $[RP]
RR3 net077 VSS 3K $[RP]
MM14 NBIAS net081 VSS VSS N W=10u L=4u M=1
MM3 net081 ENAB VSS VSS N W=2u L=2u M=1
.ENDS
********************************************************************

Please advise!