component mapping in a different way

[verylsi]

Hello All,

I recently encountered a code where components are mapped in the following mentioned manner..

It looks wonderful as it does not needs component declaration and port mapping alone is enough..

My question is how good is this practice .. and any comment on this is more than welcome.

Architecture rtl of ABC is
begin

CrcInst : entity work.Crc
   port map( 
        clk => clk,
        reset => reset,
        Sync => Sync,
        sw => sw,        
        Crc => Crc,
        dataRecord => Data0,
        dataOut => crcData
);

 

[TrickyDicky]

This feature was introduced in VHDL1993. It is great because the compiler will compare the mapping directly to the entity, rather than the compiler checking the component (which matches) then the elaborator checking the component to the entity and it cant find a match (and this is 20 minutes after you pressed compile!)

This is called direct instantiation, and I would highly recommend it. It also allows you to select which architecture to use if there are several:

my_inst : entity some_lib.my_ent( select_arch )

 

[verylsi]

Thanks tricky,

I will switch to this style with immediate effect

 

[shahulakthar]

Thing is Number of lines of your code decrease.

 

[std_match]

One thing to watch out for with direct instantiation is that the component must be compiled before it is used.
With the old style, the compile order for the source files doesn't matter.

 

[TrickyDicky]

Thanks tricky,

I will switch to this style with immediate effect

Remember that if you are instantiating Verilog, AHDL or black box components in your vhdl, you still need a component declaration.

 

[verylsi]

Thank you all for your help ...