component instantiation query in verilog

[raghava216]

I am trying to instantiate a verilog module 'comp' in another.

module comp(a,b);

input [1:0] a;
output b;

// some logic

endmodule


In another module, 'my_module', lets say a, b and c are declared.
'comp' is instantiated as follows:

comp X (.a[0](a),.a[1](b),.b(c));

While compiling, I get an error with the above line of code.
Whats wrong with this?
Any idea?

 

[nisshith]

write comp X (.a({a,b}),.b(c));

 

[raghava216]

write comp X (.a({a,b}),.b(c));

Yes Got it. The inputs need to be concatenated.

But how is the order taken?

In the above example, I want to map a to a[0] and b to a[1].

Which is correct?

comp X (.a({b,a}), .b(c)); OR comp X(.a({a,b}), .b(c));

 

[nisshith]

i think comp X(.a({a,b}), .b(c)); will give the desired result. check in the RTL view.

 

[raghava216]

i think comp X(.a({a,b}), .b(c)); will give the desired result. check in the RTL view.

I wrote "comp X(.a({b,a}), .b(c));" in my code.

I am not able to see to bit level like a[0] is mapped to what and a[1] is mapped to what. But, On placing mouse pointer on the signal a(1:0), it displays "Input pin: a(1:0) => Signal b,a" in RTL view. I am using Xilinx 12.2 ISE.

So, I feel comp X(.a({b,a}), .b(c)); is correct for the case a[0] => a and a[1] => b and
comp X(.a({a,b}), .b(c)); is correct for the case a[0] => b and a[1] => a.

 

[nisshith]

it may be correct in your case. actually comp X(.a({b,a}), .b(c)) will give different results in definition "input [1:0] a" and "input [0:1] a", so whatever comes in RTL go with it. I always get confused in this.