Yes I was referring to IP cores provided by FPGA vendors and I dnt know about experienced RTL designers but I would prefer go for that as long as they are free and tested by the vendors itself.
Hi Tricky,
I was mentioning about the timing which is getting effected by combinational delay, as IP cores gives an option to add pipelining. routing delay, as you mentioned can only be improved by fitter and how the architecture of FPGA is. and my answer was specific to adder only.
thanks for correcting me.