component instantiation and synthesis

[shikharmakkar]

i am writing a vhdl code for a circuit which contains signed adders, not or operations and the inputs fed to these adders are of different bit sizes. will there be any advantage in synthesizing if I declare these adders as components and then instantiate in my code or direct instantiation would be better for better synthesis?

 

[TrickyDicky]

Im not very clear what you mean, can you give coding examples?

Synthesis flattens the heirarchy anyway, so components and just add layers to the code structure that may be unclear.

 

[verylsi]

When you are mentioning instantiation of adders as components then do you meant adder as primitive or your own separate code for adder ?

Primitives are designed to be optimized for minimum utilization of resource and meets timing all the time and as they are free it also saves the time.

 

[TrickyDicky]

Primitives are designed to be optimized for minimum utilization of resource and meets timing all the time and as they are free it also saves the time.

This is just plain wrong. Primitives are what every design is built out off. Using primitives rather than higher level components is like using assembler instead of C. You may have to use it occasionally but it is very easy to make and error and is best avoided.

 

[verylsi]

My mistake, I was about to write IP cores, by mistake I wrote primitive. My apologies.. I am editing and correcting my post/

"
When you are mentioning instantiation of adders as components then do you meant adder as ip core or your own separate code for adder ?

Cores are designed to be optimized for minimum utilization of resource and meets timing all the time and as they are free it also saves the time.

"

 

[TrickyDicky]

You're still wrong on the timing. Yes they might have some optimisation but the timing depends on whats in the chip and how the fitter can fit the design. Its quite easy to have IP cores fail timing.

 

[ads-ee]

Cores are designed to be optimized for minimum utilization of resource

Really? Just look at Opencores to find a plethora of examples that disprove this statement.

and as they are free it also saves the time.

Once again look at opencores to find examples of IP that are documented so poorly that integrating them into your design will likely take longer than designing them from scratch.

If you are referring to IP from the FPGA's own library of free cores even then I'm not entirely convinced of their inherent quality. Even the paid for ones aren't necessarily that great. I used an IP core from an FPGA vendor, where I had to help the factory debug their flawed design. I also made some suggestions to fix problems in their code after I got to see the un-encrypted module that the factory IP specialist sent as a "patch" for me to verify that they had fixed the original protocol problem.

 

[verylsi]

Yes I was referring to IP cores provided by FPGA vendors and I dnt know about experienced RTL designers but I would prefer go for that as long as they are free and tested by the vendors itself.

Hi Tricky,
I was mentioning about the timing which is getting effected by combinational delay, as IP cores gives an option to add pipelining. routing delay, as you mentioned can only be improved by fitter and how the architecture of FPGA is. and my answer was specific to adder only.

thanks for correcting me.

 

[ads-ee]

Yes I was referring to IP cores provided by FPGA vendors and I dnt know about experienced RTL designers but I would prefer go for that as long as they are free and tested by the vendors itself.

My point is don't assume the vendor has tested the IP you are buying all that well. In my experience it's more likely they tested the most basic stuff and if you go outside those boundaries or test the robustness of the design you will likely find it lacking (or completely broken).

That IP I mentioned...well I emulated, in a simulation, some random garbage on the input (like if you connected or disconnected the source signal, or the source became garbage) and the IP locked up completely. The only recovery option was to reset the IP, but how do you detect this condition, as the IP didn't indicate anything was wrong!

Regards