compile verilog in cadence

[sambhav007]

Hi,

I want to know how to compile a verilog file and simulate the design.

Thanks,
Sambhav

 

[Chethan]

Hi,
If you already have the verilog file ready, then
1) To compile verilog file, just use the command "verilog <File name>" if you have verilogXL else use the command "ncverilog <File name>" if you have ncverilog

2) To simulate the verilog file you need a test bench. It should contain all the vectors for which you want to simulate the design.

regards
Chethan

 

[haytham]

Hey
I have previous experience with cadence tools
Kindly tell us your problem in detail and then I can help u

 

[sambhav007]

Thanks.! i'll try that out.. and yeah, oncei write the test bench, i need to compile it in the same way right? and how to siimulate my test bench? is it all command interface only isnt there a graphical interface for doing the same?

 

[Chethan]

the command for simulating ur verilog test bench is same. both ncverilog and verilogxl have graphical interface. U need to invoke them in ur test bench. ur test bench shd contain all vectors for which u want to see if functionality is correct.

 

[haytham]

to invoke the gui tool of cadence, you should write "simvision" in your shell

 

[sambhav007]

The commands verilog, ncverilog, simvision do not work.. it says command not found.. probably i need to do the setup.. can anybody tell me what setup i need to do before i can use verilog xl or ncverilog..