For miller compensation with your load and UGF You need at least 9.5 mS in output stage and ~3.2 mS in input stage with 500fF compensation cap. It gives You around 350µA of input stage tail current and 1.25 mA in output stage for proper designed 2stage miller compensated opamp with cascoded first stage.
Of course You can used cascoded compsenation for better results.
If You have not any additional constraints for power consumption I woudn't recommend You any more sophisticated techniques.
I assumed situation with only capacitive load for simplicity.
Your constraints was 100dB of OL DC gain, 1 GHz of UGF and 500fF of load.
To be sure of stability second pole should be locate at 3×UGF=3GHz→18.84 Grad/s. For 500fF of Cload it gives a 9.42mS of output stage transconductance. The output transistor has to be matched with loading first stage current mirror, so I assumed inversion coefficient around 10 what gives me gm/Id=7.9 (slope factor for technology I assumed to be equal 1.3). Above numbers results with output stage current of 1.2mA.
To calculate the first stage current once again I used UGF constraint together with 500fF compensation capacitor assumptions to obtain a 3.14 mS of input transistor transconductance. 100dB open loop gains gives 5 decades distance between UGF and dominant pole. This is achievable with cascoded first stage and 40dB of intrinsic transistors gain.
Assuming moderate inversion for input diff pair (gm/Id=18 resulting of IC around 1) it gives me 175µA for each mosfet resulting in 350µA of tail current.
Of course above are the only roughly hand calculations.
To get dimensions You have to check current gain factors in your process documentation and calculate technology current Ispec=2nKVt²W/L for both p and nmosfets, and also rememeber or simulate short channel effects influencing the mosfet parametrers.
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