Compensation technique for two stage opamp

[electronics_rama]

Hello,

I'm designing a two stage opmap. From the specification, the DC gain should be 100db and unity gain bandwidth should be 1GHz. I was trying to implement it with Folded cascode first stage and miller compensation between the two stages. I'm not able to achieve the specified bandwidth. All I could reach was near to 250MHz with a gain of around 97db.

Can you guys please help me here?

Will miller compensation work for higher bandwidth designs or should I go for different type of compensation?

-Rama

 

[AMS012]

Miller compensation works but you will have to burn a lot of current in the first stage. Have you thought about the feed forward compensated amplifier topology which will be more power efficient for the spec you have mentioned? BTW, what application is the opamp being used for?

 

[electronics_rama]

I'm using this opamp for the variable gain amplifier application. I have drive resistive load.How about current buffering technique for compensation??

 

[raduga_in]

Hi electronics_rama

What technology are you using ?

Regards

Raduga

 

[AMS012]

Yes, the current buffering technique for compensation gives a huge advantage as far as the stability of the loop is concerned (This technique eliminates the RHP zero that occurs in case of miller compensation and is very similar to having a zero nullifying resistor in miller compensation).

But, I am not very sure about the power consumption as compared to its miller compensated counterpart. I think, it will have more or less the same current consumption as miller compensation for same UGB. Good technique and is worth trying.

 

[Dominik Przyborowski]

Without any information about load of the amplifier is hard to say anything.

 

[electronics_rama]

I'm using GF 180nm

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The load is 500fF. And the first stage is folded cascode stage. So is it possible to compensate with just miller cap between high impedance folded cascode stage and the low impedance second stage?
I remember reading somewhere, suggesting not to go for a simple Miller compensation between high impedance nodes. So, should I go for other compensation techniques?

-Rama

 

[Dominik Przyborowski]

For miller compensation with your load and UGF You need at least 9.5 mS in output stage and ~3.2 mS in input stage with 500fF compensation cap. It gives You around 350µA of input stage tail current and 1.25 mA in output stage for proper designed 2stage miller compensated opamp with cascoded first stage.

Of course You can used cascoded compsenation for better results.
If You have not any additional constraints for power consumption I woudn't recommend You any more sophisticated techniques.

 

[electronics_rama]

Hello Domnik,

I tried this approach. But my calculated output stage current was near to 500uA to drive a minimum load of 1Kohms. So, to achieve a gm near to 10mS, I had to go with very large devices and I faced the problem of very high cgd of the second stage. Can you please elaborate on how you decided a current of 1.25mA for the second stage? Also, I'm still not clear on this approach!

In your approach, you are not keeping second stage gm very high compared to the first stage! So, the right half plane zero we have to cancel. To cancel this we need a value of resistance which introduces third pole and it is reducing my bandwidth. Please suggest how to go ahead!

-Rama

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Also, Can you please tell me how you calculated current values for the first and second stages?

 

[AMS012]

The problem with miller compensation in high speed amplifiers is that the first pole (the first stage output pole) gets pushed to very low frequency and hence it will reduce the bandwidth of the opamp.

1. One thing you can try is to burn more current in the first stage to push the first pole out which helps you increase the bandwidth.
2. Try combining the tail current sources of the differential pair of the folded cascode stage. That will push the first pole out. You loose a little on the DC gain which you should be able to achieve in the second stage if required. (Ideally, in the miller compensated opamps, the stage, usually the output stage, which is bypassed at higher frequencies by the compensating capacitor should have a higher DC gain. This will help you achieve a better phase margin as well). The idea is to give up a little on the first stage gain to achieve the required bandwidth.

 

[electronics_rama]

For miller compensation with your load and UGF You need at least 9.5 mS in output stage and ~3.2 mS in input stage with 500fF compensation cap. It gives You around 350µA of input stage tail current and 1.25 mA in output stage for proper designed 2stage miller compensated opamp with cascoded first stage.

Of course You can used cascoded compsenation for better results.
If You have not any additional constraints for power consumption I woudn't recommend You any more sophisticated techniques.

Hello Domnik,

I tried to design with the parameters you told. Also I have used a resistor to cancel the right half plane zero, which comes around 4Kohms. I could reach a bandwidth of 500MHz which was not possible with my previous approach. I'm very curious to know about how you are suggesting the value of current that I should use. Previously I was getting the value of current based on the slew rate specifications, and having tail current value as 25u and second stage current as 500u.

Please please tell me how did you give those values.

-Regards,
Rama

 

[Dominik Przyborowski]

I assumed situation with only capacitive load for simplicity.
Your constraints was 100dB of OL DC gain, 1 GHz of UGF and 500fF of load.
To be sure of stability second pole should be locate at 3×UGF=3GHz→18.84 Grad/s. For 500fF of Cload it gives a 9.42mS of output stage transconductance. The output transistor has to be matched with loading first stage current mirror, so I assumed inversion coefficient around 10 what gives me gm/Id=7.9 (slope factor for technology I assumed to be equal 1.3). Above numbers results with output stage current of 1.2mA.
To calculate the first stage current once again I used UGF constraint together with 500fF compensation capacitor assumptions to obtain a 3.14 mS of input transistor transconductance. 100dB open loop gains gives 5 decades distance between UGF and dominant pole. This is achievable with cascoded first stage and 40dB of intrinsic transistors gain.
Assuming moderate inversion for input diff pair (gm/Id=18 resulting of IC around 1) it gives me 175µA for each mosfet resulting in 350µA of tail current.

Of course above are the only roughly hand calculations.
To get dimensions You have to check current gain factors in your process documentation and calculate technology current Ispec=2nKVt²W/L for both p and nmosfets, and also rememeber or simulate short channel effects influencing the mosfet parametrers.

 

[electronics_rama]

I assumed situation with only capacitive load for simplicity.
Your constraints was 100dB of OL DC gain, 1 GHz of UGF and 500fF of load.
To be sure of stability second pole should be locate at 3×UGF=3GHz→18.84 Grad/s. For 500fF of Cload it gives a 9.42mS of output stage transconductance. The output transistor has to be matched with loading first stage current mirror, so I assumed inversion coefficient around 10 what gives me gm/Id=7.9 (slope factor for technology I assumed to be equal 1.3). Above numbers results with output stage current of 1.2mA.
To calculate the first stage current once again I used UGF constraint together with 500fF compensation capacitor assumptions to obtain a 3.14 mS of input transistor transconductance. 100dB open loop gains gives 5 decades distance between UGF and dominant pole. This is achievable with cascoded first stage and 40dB of intrinsic transistors gain.
Assuming moderate inversion for input diff pair (gm/Id=18 resulting of IC around 1) it gives me 175µA for each mosfet resulting in 350µA of tail current.

Of course above are the only roughly hand calculations.
To get dimensions You have to check current gain factors in your process documentation and calculate technology current Ispec=2nKVt²W/L for both p and nmosfets, and also rememeber or simulate short channel effects influencing the mosfet parametrers.

Hello Domnik,

This is a great knowledge for me! I could not find this type of methodology for the design in any text books. All I was doing was as follows,
1. Obtain the compensation capacitor value based on the assumption of putting the right half plane zero to infinity. For this I have to keep second stage gm to be 10 times of first stage.
1. Obtain the tail current value of the first stage by slew rate specification and obtained compensation capacitor value.
2. Get the value of current for the second stage based on the lowest load resistor I have to drive.
3. Based on UGF obtain the value of gm of first stage.
Now with all these obtained values, I was calculating the W/L of transistors. This worked fine for low frequencies of UGF, say 5 MHz. But for very high frequencies, this method is not working.

Do you think I am doing wrong in the above steps?

Your explanation seems to be very interesting for me! Can you please help me in suggesting some reference for IC and gm/ID based design techniques, so that I will change my approach in the design

 

[Dominik Przyborowski]

David Binkley Tradeoffs... is one of the most completely position which focusing both on technology and circuits, I think. You can also check P. Jesper book and Enz, Vittoz book about modelling.

In fact I don't use typical gm/Id methodology but my experience, which part of it is showed in my phd thesis ((un)fortunately written in polish)

 

[electronics_rama]

I went through the theory behind gm/ID and IC based design techniques. I exactly understood how you derived those values now. I feel I should stick with this methodology. I'm bit not sure how to apply this methodology for designing the gain stage in folded cascode! I can derive the values of W/L for the diff pair of first stage. But what about the transistors used in folded cascode stack? Please guide me how to go ahead here!

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Thanks for suggesting that book; Tradeoffs and Optimization in Analog CMOS Design. Got the copy. Started reading. You are really helpful. Thanks a lot!

-Rama

 

[electronics_rama]

I followed the gm/id methodology for the design. Theoretically I should get the bandwidth I was expecting with second pole sitting near 3GHz. But my second pole is appearing near 200MHz. I'm seeing this pole because of Common mode feedback circuit? I'm not sure about this! Any suggestion?