When the conversion begins, the output of the SAR comparator, which indicates whether the analog input is greater than (high) or less than (low) each successive voltage from the internal resistor ladder, appears at the DO line on each falling edge of the clock. This data is the result of the conversion being shifted out (with the MSB coming first) andcan be read by the processor immediately.
7. After 8 clock periods the conversion is completed. The SAR status line returns low to indicate this 1⁄2 clock cycle later.