[SOLVED] Comparison between std+

[Samran]

VHDL: Comparison between vectors

Hi all,

I'm working on simulating a VHDL design using a self-checking testbench. As part of the error checking, I compare two values: one that is the expected value and one that is the received value. Both of these values are 16-bit std_logic_vectors and are members of arrays of 32 entries.

In the design, I send out a value that is then sent back through other means. The sent value comes from TriggerInArray(0) and the received value is read in to TriggerOutArray(0). I then compare TriggerInArray(0) and TriggerOutArray(0) and print "success" or "failure" and the expected and received values. In this test, I expect and receive the 16-bit hex value 0025, but for some reason the 0025 in TriggerInArray(0) does not equal the 0025 in TriggerOutArray(0).

Code excerpt:

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
 
procedure CheckTriggers is
    variable TriggerInArray : STD_ARRAY;
    variable TriggerOutArray : STD_ARRAY;
    variable val : std_logic_vector (15 downto 0) := x"0000";
    variable bval : boolean;
    variable mask : std_logic_vector(15 downto 0) := x"0000";
begin
        **Stuff to send values**
    
        --Retrieve values: --
    for j in 0 to 15 loop
       mask := std_logic_vector(ieee.numeric_std.to_unsigned(2**j, 16));
       bval := IsTriggered(x"60", mask);
       val := std_logic_vector(shift_left(ieee.numeric_std.unsigned(to_std(bval)),j));
       TriggerOutArray(0) := TriggerOutArray(0) or val;
    end loop;
    writeline(output, msg_line);
    write(msg_line, STRING'("Trigger 0 received: "));
    hwrite(msg_line, TriggerOutArray(0));
    writeline(output, msg_line);
 
    if TriggerInArray(0) = TriggerOutArray(0) then
        write(msg_line, STRING'("SUCCESS: Expected "));
        passtemp := passtemp + 1;
    else
        write(msg_line, STRING'("FAILURE:  Expected "));
        failtemp := failtemp + 1;
    end if;
    hwrite(msg_line, TriggerInArray(0));
    write(msg_line, STRING'(", received: "));
    hwrite(msg_line, TriggerOutArray(0));
    writeline(output, msg_line);
 
end procedure CheckTriggers;

---

The output I see in the simulation is as follows:

Trigger 0 received: 0025
FAILURE:  Expected 0025, received: 0025

To answer a couple potential questions about the code I omitted:

• IsTriggered is a function that checks a particular bit on the incoming value. It returns a boolean.
• to_std is a function I wrote to convert a boolean value into a 16-bit std_logic_vector
• In this design, I use both numeric_std and std_logic_arith. This is necessary because of the way other pieces of the program work and I cannot omit one or the other (I tried and it broke a part of the program that I'm not allowed to change).

Thanks in advance for any help! I'm officially stumped on this one.

 

[TrickyDicky]

Ok - edit - Must read all of post...

Because you are using hwrite, it is probably converting any meta values (like 'X' or 'U' on single bits) to 0. Are you sure they are exactly equal? try writing them as binary values instead, or check the waveform.

 

[K-J]

Re: VHDL: Comparison between vectors

Thanks in advance for any help! I'm officially stumped on this one.

1. But a breakpoint at line 29 ("if TriggerInArray(0) = TriggerOutArray(0) then"). Then take a look at the value of the variables 'TriggerInArray(0)' and 'TriggerOutArray(0)', then you will see how they are different.

2. Trace back to see how the deviant variable got it's value. Repeat this until you find the root cause. This process is called debugging.

I'll also note that there appears to be no initializer for 'TriggerOutArray(0)' which, if true, means that you're using it before it has been initialized in the statement on line 22 ("TriggerOutArray(0) := TriggerOutArray(0) or val;") so the likely cause is simply that you did not initialize TriggerOutArray at any point.

Kevin Jennings

 

[Samran]

Aha! There it is.

TrickyDicky - You were correct that hwrite was converting the meta value "U" to 0. Being more of a Verilog person, I was unaware of the nuances of write and hwrite. Using

write(msg_line, STD_LOGIC_VECTOR'(TriggerOutArray(0)));

instead of

hwrite(msg_line, TriggerOutArray(0));

allowed me to see that all of the '0' values that were being assigned to "val" were being replaced by 'U' in the line

TriggerOutArray(0) := TriggerOutArray(0) or val;

K-J - Therein lies the problem. Since I was not initializing TriggerOutArray, all of the '0' bits in "val" were being replaced by 'U' in line 22. To fix this, I added a line in an earlier loop that initialized each value in TriggerOutArray to x"0000" and I'm now getting true '0' and '1' values on all the bits.

Code changed:

for k in 0 to 31 loop
	val := val + 37;
	TriggerInArray(k) := val;
end loop;

became:

for k in 0 to 31 loop
	val := val + 37;
	TriggerInArray(k) := val;
	TriggerOutArray(k) := x"0000";
end loop;

Thanks for your help!