yuenkit
Advanced Member level 4
std_match
1. if i want to do somthing like casex in verilog, what should i do?
2. is std_ulogic type synthesizable?
3. i wish to make a look up table.
part of the my code is something like
case A is
when "1---" => out <= "0001"
or
i should introduce an immediate variable
var <= A & "1000";
case var is
when "1000 => out <= "0001"
which one is better?, pls give suggestion. Thanks
1. if i want to do somthing like casex in verilog, what should i do?
2. is std_ulogic type synthesizable?
3. i wish to make a look up table.
part of the my code is something like
case A is
when "1---" => out <= "0001"
or
i should introduce an immediate variable
var <= A & "1000";
case var is
when "1000 => out <= "0001"
which one is better?, pls give suggestion. Thanks