compare with don't care condition in VHDL

[yuenkit]

std_match

1. if i want to do somthing like casex in verilog, what should i do?

2. is std_ulogic type synthesizable?

3. i wish to make a look up table.

part of the my code is something like

case A is
when "1---" => out <= "0001"

or

i should introduce an immediate variable
var <= A & "1000";

case var is
when "1000 => out <= "0001"

which one is better?, pls give suggestion. Thanks

 

[Ace-X]

vhdl std_match

1. if i want to do somthing like casex in verilog, what should i do?

There is case in VHDL if you want to use process. Also, you can make conditional assignments outside of process, using keyword "when".

2. is std_ulogic type synthesizable?

Yes. The special table is used to re-compile 9 possible values of std_ulogic to '0', '1' and 'X'.

3. i wish to make a look up table.
part of the my code is something like
case A is
when "1---" => out <= "0001"

Wrong! Don't care ('-') of std_logic is different with classical idea of don't care.

or
i should introduce an immediate variable
var <= A & "1000";

Depends on compiler. Some old synthesizers can introdice additional AND stage, which is not necessary.

case var is
when "1000 => out <= "0001"

This one will work OK. Every synthesizer simplifies logic of case statement. Also, you can try to use "if" statement.

Also, I would recommend you to read manual of your synthesizer - most of these questions are answered there.

 

[xlnx]

std_match vhdl

Hi!
You can also use std_match function from ieee.numeric_std package

below is example code from my design .It is an priority encoder

if std_match(dane_24(23 downto 0),"-----------------------1")then
decoded<="00001";
elsif std_match(dane_24(23 downto 0),"----------------------1-")then
decoded<="00010" ;
elsif std_match(dane_24(23 downto 0),"---------------------1--")then
decoded<="00011";
elsif std_match(dane_24(23 downto 0),"--------------------1---")then
decoded<="00100";
elsif std_match(dane_24(23 downto 0),"-------------------1----")then
decoded<="00101";
elsif std_match(dane_24(23 downto 0),"------------------1-----")then
decoded<="00110";
elsif std_match(dane_24(23 downto 0),"-----------------1------")then
decoded<="00111";
elsif std_match(dane_24(23 downto 0),"----------------1-------")then
decoded<="01000";
elsif std_match(dane_24(23 downto 0),"---------------1--------")then
decoded<="01001";
elsif std_match(dane_24(23 downto 0),"--------------1---------")then
decoded<="01010";
elsif std_match(dane_24(23 downto 0),"-------------1----------")then
decoded<="01011";
elsif std_match(dane_24(23 downto 0),"------------1-----------")then
decoded<="01100";
elsif std_match(dane_24(23 downto 0),"-----------1------------")then
decoded<="01101";
elsif std_match(dane_24(23 downto 0),"----------1-------------")then
decoded<="01110";
elsif std_match(dane_24(23 downto 0),"---------1--------------")then
decoded<="01111";
elsif std_match(dane_24(23 downto 0),"--------1---------------")then
decoded<="10000";
elsif std_match(dane_24(23 downto 0),"-------1----------------")then
decoded<="10001";
elsif std_match(dane_24(23 downto 0),"------1-----------------")then
decoded<="10010";
elsif std_match(dane_24(23 downto 0),"-----1------------------")then
decoded<="10011";
elsif std_match(dane_24(23 downto 0),"----1-------------------")then
decoded<="10100";
elsif std_match(dane_24(23 downto 0),"---1--------------------")then
decoded<="10101";
elsif std_match(dane_24(23 downto 0),"--1---------------------")then
decoded<="10110";
elsif std_match(dane_24(23 downto 0),"-1----------------------")then
decoded<="10111";
elsif std_match(dane_24(23 downto 0),"1-----------------------")then
decoded<="00000";
end if;

Regards Martin (PL)

 

[Ace-X]

vhdl dont care

Hi!
You can also use std_match function from ieee.numeric_std package

below is example code from my design .It is an priority encoder

if    std_match(dane_24(23 downto 0),"-----------------------1")then
				decoded<="00001";
elsif std_match(dane_24(23 downto 0),"----------------------1-")then
				decoded<="00010" ;
...skipped...
elsif std_match(dane_24(23 downto 0),"1-----------------------")then
				decoded<="00000";
end if;

And what should be assigned to signal "decoded" in case when all bits of "dane_24" are 0? You will get unnecessary latches, just because you missed one possible value: "all 0".

As to priority encoder, I would prefer combinational statement, like this:

decoded <= "00001" when dane_24(0) = '1' else
          "00010" when dane_24(1) = '1' else
          ......            
          "10111" when dane_24(22) = '1' else
          "00000";

 

[xlnx]

vhdl casex

Yes of course my fault
it should be:
.....
elsif std_match(dane_24(23 downto 0),"1-----------------------")then
decoded<="00000";
else decoded<="00000";
end if;

Regards Martin (PL)

Added after 23 minutes:

Ace-X I have little offtopic question :
Are any restrictions to check priority on signal edge?
Checked signal is stable long before and long after this edge,
or rather I should use some level sensitive logic?

 

[Ace-X]

dont care in vhdl

Are any restrictions to check priority on signal edge?
Checked signal is stable long before and long after this edge,
or rather I should use some level sensitive logic?

Priority encoder is pure combinational logic, so it just encodes currrent input value. It is up to you how you will latch/sample its output.

 

[chitra ranganath]

hi
can u pls send me vhdl code to compare n bytes like for ex:
101010101 compared with 10101000