compare with don't care condition in VHDL

std_match

1. if i want to do somthing like casex in verilog, what should i do?

2. is std_ulogic type synthesizable?

3. i wish to make a look up table.

part of the my code is something like

case A is
when "1---" => out <= "0001"

or

i should introduce an immediate variable
var <= A & "1000";

case var is
when "1000 => out <= "0001"

which one is better?, pls give suggestion. Thanks

vhdl std_match

yuenkit said:

1. if i want to do somthing like casex in verilog, what should i do?

Click to expand...

There is case in VHDL if you want to use process. Also, you can make conditional assignments outside of process, using keyword "when".

yuenkit said:

2. is std_ulogic type synthesizable?

Click to expand...

Yes. The special table is used to re-compile 9 possible values of std_ulogic to '0', '1' and 'X'.

yuenkit said:

3. i wish to make a look up table.
part of the my code is something like
case A is
when "1---" => out <= "0001"

Click to expand...

Wrong! Don't care ('-') of std_logic is different with classical idea of don't care.

yuenkit said:

or
i should introduce an immediate variable
var <= A & "1000";

Click to expand...

Depends on compiler. Some old synthesizers can introdice additional AND stage, which is not necessary.

yuenkit said:

case var is
when "1000 => out <= "0001"

Click to expand...

This one will work OK. Every synthesizer simplifies logic of case statement. Also, you can try to use "if" statement.

Also, I would recommend you to read manual of your synthesizer - most of these questions are answered there.

std_match vhdl

Hi!
You can also use std_match function from ieee.numeric_std package

below is example code from my design .It is an priority encoder

if std_match(dane_24(23 downto 0),"-----------------------1")then
decoded<="00001";
elsif std_match(dane_24(23 downto 0),"----------------------1-")then
decoded<="00010" ;
elsif std_match(dane_24(23 downto 0),"---------------------1--")then
decoded<="00011";
elsif std_match(dane_24(23 downto 0),"--------------------1---")then
decoded<="00100";
elsif std_match(dane_24(23 downto 0),"-------------------1----")then
decoded<="00101";
elsif std_match(dane_24(23 downto 0),"------------------1-----")then
decoded<="00110";
elsif std_match(dane_24(23 downto 0),"-----------------1------")then
decoded<="00111";
elsif std_match(dane_24(23 downto 0),"----------------1-------")then
decoded<="01000";
elsif std_match(dane_24(23 downto 0),"---------------1--------")then
decoded<="01001";
elsif std_match(dane_24(23 downto 0),"--------------1---------")then
decoded<="01010";
elsif std_match(dane_24(23 downto 0),"-------------1----------")then
decoded<="01011";
elsif std_match(dane_24(23 downto 0),"------------1-----------")then
decoded<="01100";
elsif std_match(dane_24(23 downto 0),"-----------1------------")then
decoded<="01101";
elsif std_match(dane_24(23 downto 0),"----------1-------------")then
decoded<="01110";
elsif std_match(dane_24(23 downto 0),"---------1--------------")then
decoded<="01111";
elsif std_match(dane_24(23 downto 0),"--------1---------------")then
decoded<="10000";
elsif std_match(dane_24(23 downto 0),"-------1----------------")then
decoded<="10001";
elsif std_match(dane_24(23 downto 0),"------1-----------------")then
decoded<="10010";
elsif std_match(dane_24(23 downto 0),"-----1------------------")then
decoded<="10011";
elsif std_match(dane_24(23 downto 0),"----1-------------------")then
decoded<="10100";
elsif std_match(dane_24(23 downto 0),"---1--------------------")then
decoded<="10101";
elsif std_match(dane_24(23 downto 0),"--1---------------------")then
decoded<="10110";
elsif std_match(dane_24(23 downto 0),"-1----------------------")then
decoded<="10111";
elsif std_match(dane_24(23 downto 0),"1-----------------------")then
decoded<="00000";
end if;

Regards Martin (PL)

vhdl dont care

xlnx said:

Hi!
You can also use std_match function from ieee.numeric_std package

below is example code from my design .It is an priority encoder

Code:

if    std_match(dane_24(23 downto 0),"-----------------------1")then
				decoded<="00001";
elsif std_match(dane_24(23 downto 0),"----------------------1-")then
				decoded<="00010" ;
...skipped...
elsif std_match(dane_24(23 downto 0),"1-----------------------")then
				decoded<="00000";
end if;

Click to expand...

And what should be assigned to signal "decoded" in case when all bits of "dane_24" are 0? You will get unnecessary latches, just because you missed one possible value: "all 0".

As to priority encoder, I would prefer combinational statement, like this:

vhdl casex

Yes of course my fault
it should be:
.....
elsif std_match(dane_24(23 downto 0),"1-----------------------")then
decoded<="00000";
else decoded<="00000";
end if;

Regards Martin (PL)

Added after 23 minutes:

Ace-X I have little offtopic question :
Are any restrictions to check priority on signal edge?
Checked signal is stable long before and long after this edge,
or rather I should use some level sensitive logic?

dont care in vhdl

xlnx said:

Are any restrictions to check priority on signal edge?
Checked signal is stable long before and long after this edge,
or rather I should use some level sensitive logic?

Click to expand...

Priority encoder is pure combinational logic, so it just encodes currrent input value. It is up to you how you will latch/sample its output.

hi
can u pls send me vhdl code to compare n bytes like for ex:
101010101 compared with 10101000