swolf
Newbie level 6
I am designing a dynamic comparator which is composed of a preamp and a latch, i.e. the attached figure. the input signal is differential and it is sampled and subtracts Vthreshold with a swithed capacitance circuit (omitted in the figure).
the process i use is 0.18um, and the parameter Vth0=0.4.
the question is:
is this architecture appropriate when it is working under 1.8V power supply? some other para. are: Vcm=0.9V, vref+=1.2, vref-=0.6, and the threshold voltage is +/-5/8Vref, +/-3/8Vref, +/-1/8Vref respectively.
in my opinion, because the in+ or in- may be as low as 0.6V (or even lower), and the common mode voltage of input MOSes should be larger than the value of Vth +2Vod, it is difficult to design the para. of MOSes to satisfy that. however some ieee papers just utilize this architecture which are also under 1.8V power supply. why?
could anyone give me some hints?
thank you in advance!
the process i use is 0.18um, and the parameter Vth0=0.4.
the question is:
is this architecture appropriate when it is working under 1.8V power supply? some other para. are: Vcm=0.9V, vref+=1.2, vref-=0.6, and the threshold voltage is +/-5/8Vref, +/-3/8Vref, +/-1/8Vref respectively.
in my opinion, because the in+ or in- may be as low as 0.6V (or even lower), and the common mode voltage of input MOSes should be larger than the value of Vth +2Vod, it is difficult to design the para. of MOSes to satisfy that. however some ieee papers just utilize this architecture which are also under 1.8V power supply. why?
could anyone give me some hints?
thank you in advance!
