Comparator gain question for high speed SAR

[sethtalk]

comparator gain question for high speed sar

hi,
in traditional low speed high resolution sar adc, the comparator adopt OOS　or IOS pre-amplifier stages to boost comparator gain
and then it can meet high resolution requirement, but i find papers which is about high speed(10b or more) sar design, the comparator only adopt a 1 stage pre-amplilier + latch architecture , my question is why the comparator gain can meet high resolution spec?

i think redundancy method is part reason, but in the final decision step in sar adc operation, the comparator still need to face the in voltage is only few LSB
voltage...　
hope senior can give me a few instructions, thanks very much!!

 

[dick_freebird]

Re: comparator gain question for high speed sar

Not sure what OOS / IOS mean.

Latching comparators' regenerative action creates a high
stage gain at the point of decision. DC gain through the
front end is low.

You have two problems in a SAR ADC comparator.One
is the need for gain to be high such that a LSB can
be resolved. The other is for low-overdrive (sub-LSB)
propagation delay to be less than the allowed amount
(bit time minus DAC settling minus SAR logic delay ...).
So you need a good front end gain to make the back
end snappy.

 

[sethtalk]

Re: comparator gain question for high speed sar

hi,dick_freebird,

your reply help me a lot, thanks!
(IOS : i means input offset cancellation ...)
i think a conclusion:
latch comparator gain is infinite , the key is speed, that is why we always need some pre-amplifier
stages to boost LSB voltage , largre input make latch comparator response faster,
in nano meter (90nm or below) high speed sar , the latch comparator speed boost, and assisted
with asynchronous+redundancy design, i always see 1 pre-amplifier stage+latch comparator architecture,
even in 12b resolution spec