comparator design problem

[hunk]

the comparator has a good offset(≤1mv) and a fast response(maybe ) to the input pulse, for instanse, when the input- is holded at COM, the input+ is a step pulse very fast the delay of output is about 200ns.

When the input- is holded, the input+ changes very slowly, the switching point equals the voltage of input-. But if the speed of input+ increased slightly(about 1v/us) the switching point will diffrent from the input- about 100mv. why isn't equals input-. so larger offset? how can i elimlate this offset?

thanks in advance!!

 

[alasliu]

may be simulation problem

 

[aryajur]

Hello Hunk,
I think your simulation makes sense because as you said your prop delay is 200nS so if you increase the speed of the input+ to 1V/us then the time it takes the output to start switching would be around 200nS and by that time input+ would have crossed input- by 200mV.