Well if you really want to be more formal and need to design with proper hierarchy, then do so. Otherwise first I recommend you to write one single vhd file with simple FSM for tx and another FSM for Rx.
1) create a vhd file
2) write an FSM for Tx with 3 states say "start_bit,data_bit,stop_bit".
a) In state1, use a counter with counts till 1 baud rate clock period(1 bit period = sys_clk/9600 = 1 bit period).Drive the Tx line to active High
b) Use same counter logic in state 2 and send 8-bits one by one like a parallel to serial convertor.
c) Use again same count logic and drive tx active high as stop bit.
Similarly you need to write receiver logic exactly like shown above. 1 exceptional is here you are doing serial to parallel instead
Test this logic first in FPGA board1 by looping\shorting Tx and rx. If you are able to decode data in Rx part, then you can plan for target board. Also once you become stable with basic driver logic code, you can build design with tx buffer and rx buffer and even add parity etc....