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communication problem between two FPGA board through UART

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Apr 23, 2009
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UART -help

Hello ,
I m trying to communicate between two FPGA board through UART ,
a constad data of 16 byte is being transmitted from the board1 with a baudrate say 9600.
and the other board is also configured to receive at the same baud rate,
i m trying to receive the 16 bytes of data and transmit the same back with no (/ simple ) processing .

Can anybody help me in this regard. please reply to have a further briefing on this .

thanks in advance.

UART -help

Well I can give you some guidelines, first of all of course you will put the regular two FF (metastability Filter), then some switch detection circuit, i.e. a circuit which will determine if data changed from zero to one, you logic must work at at least double the clock speed according to your logic output (divided by the clock speed) you may determine the data is zero or one.
Start bit will always be your guide
you will need FSM and counter a very simple circuit.
I usually make the clock like 100 * 9600 hz or something so that I can read data at speed up to 50 * 9600 ..
That's it, as for transition detection search the internet you will find plenty out there.
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Re: UART -help

Attached you will find a byte based serial input and output based components, including test benches for it.
You can either use it directly (sending/receiving 16 single bytes), or you could modify it to input/output a 128 bit (==16 bytes) bit stream....
im using spartan 3A/3AN board for writing UART code i was using xilinxs protype text book by pong p chu can any one help me in code i want to write separate code for each module like tx module rx module fifo module and baud rate module

Well if you really want to be more formal and need to design with proper hierarchy, then do so. Otherwise first I recommend you to write one single vhd file with simple FSM for tx and another FSM for Rx.
1) create a vhd file
2) write an FSM for Tx with 3 states say "start_bit,data_bit,stop_bit".
a) In state1, use a counter with counts till 1 baud rate clock period(1 bit period = sys_clk/9600 = 1 bit period).Drive the Tx line to active High
b) Use same counter logic in state 2 and send 8-bits one by one like a parallel to serial convertor.
c) Use again same count logic and drive tx active high as stop bit.

Similarly you need to write receiver logic exactly like shown above. 1 exceptional is here you are doing serial to parallel instead
Test this logic first in FPGA board1 by looping\shorting Tx and rx. If you are able to decode data in Rx part, then you can plan for target board. Also once you become stable with basic driver logic code, you can build design with tx buffer and rx buffer and even add parity etc....

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