Use a combinational multiplexer...
Code Verilog - [expand] |
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| always @* begin
case ({x,y})
2'b10 : total_result <= result1;
2'b01 : total_result <= result2;
default : total_result <= 0; // or whatever constant you want
endcase
end |
I also don't see the point in distinguishing that the output can't be either RAM when {x,y} == 2'b00 it shouldn't matter what the output is, as you probably shouldn't be looking at the total_result value when you have that condition.