i think parmod is right that glistces can occur regarding skew we can take care while doing CTS. Anyways some skew still will be there after CTS on the basis of diffrent PVT but that we can model in Gate level simulations and STaA
If derived clocks are required in a design (clock enables should be preferred as far as possible), they should be finally sourced from a flip-flop clocked by the main clock. This doesn't avoid timing issues when crossing clock domains but removes glitches.
Thanks for the promp reply...
so conclusion is if we have comb ckt in the clock path clock glitch may occure in certain conditions and also clock skew will be there.