combinatorial ckt in clock path

[alam.tauqueer]

Can anyone tell me

What will happen(effect) if combinatorila ckt are present in the clock path of a design.

Regards
Tauqueer

 

[pramodm]

clock glitchs may occurs on certain situations,

so many avoid combinational logic on clock patchs

 

[neetinsingh]

It will add clock skew which cuases timing issue and also cause controlabilty issue in DFT implementation........

 

[vikas_lakhanpal27]

i think parmod is right that glistces can occur regarding skew we can take care while doing CTS. Anyways some skew still will be there after CTS on the basis of diffrent PVT but that we can model in Gate level simulations and STaA

 

[FvM]

If derived clocks are required in a design (clock enables should be preferred as far as possible), they should be finally sourced from a flip-flop clocked by the main clock. This doesn't avoid timing issues when crossing clock domains but removes glitches.

 

[alam.tauqueer]

Thanks for the promp reply...
so conclusion is if we have comb ckt in the clock path clock glitch may occure in certain conditions and also clock skew will be there.

Regards,
Tauqueer