Combinational latch?????????

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Hi,

Below is an example of combinational latch:

Code: 
module com_latch (a, b, c);

input a, b;
output c;

reg c;

always @(a or b)
begin
      if(a) 
            c <= b; // no else statement
end

endmodule

This piece of verilog code will infer a latch or combinational latch.
This is not a good coding style. Unless, u intent to do this.

Hope it helps.
 

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