Combinational latch?????????

[verilog_always]

What does combinational Latch mean???

 

[no_mad]

Hi,

Below is an example of combinational latch:

module com_latch (a, b, c);

input a, b;
output c;

reg c;

always @(a or b)
begin
      if(a) 
            c <= b; // no else statement
end

endmodule

This piece of verilog code will infer a latch or combinational latch.
This is not a good coding style. Unless, u intent to do this.

Hope it helps.