Combinational feedback loop

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Jyotshna_Sharma

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combinational feedback

If any one can suggest me how to know the exact clock to pad delay through a combinational feedback loop.
]The feedback loop is not inferred but is purposly included.The tool that I am using is XST.
How to constrain So that I will get the delay.
 

combinational feedback loop

Combinational feedback circuits (latches) aren't well supported by most synthesis tools, but I don't know in special regarding the Xilinx tool. Some tools are using an option analyze combinational loops as synchronous circuit and calculate a maximum clock freuency for it. It would give a rough estimation of loop delay.
 

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