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Coding the Logic Minimization

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sudhirkv

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Hi everybody....

I need to generate reset pulse where it goes low for 100 milli seconds and goes high for another 10ms and then goes low for another 10 ms and then goes high after that.

I have written the code as below. its working fine.

But i want to know any other way to code for this task.

always @ (posedge ClkIn or negedge n_Reset)

begin

if(!n_Reset)
begin
n_resetout <= 1'b0;
resetcount <= 24'b0;
end

else if(resetcount < 24'h7A120)
begin
n_resetout <= 1'b0;
resetcount <= resetcount+1;
end

else if(resetcount >= 24'h7A120 && resetcount < 24'h86470)
begin
n_resetout <= 1'b1;
resetcount <= resetcount+1;
end

else if((resetcount >= 24'h86470) && (resetcount < 24'h100590))
begin
n_resetout <= 1'b0;
resetcount <= resetcount+1;
end
else if(resetcount >= 24'h100590)
n_resetout <= 1'b1;



end
 

Iouri

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Logic Minimization

you can use state machine also
 

sudhirkv

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Re: Logic Minimization

if we use the state machine there also we have to use counters to count.

How to optimize the counting technique
 

ls000rhb

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Logic Minimization

The max time step is 100ms, so the counter size is determined by 100ms, other time steps can reuse this counter.
BR.
ls000rhb
 

lubee

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Logic Minimization

using FSM can reduce the width of the counter, so it is a good way to reduce the logcal resources.
 

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