Re: input
i have written the file as follows
module inputdata(data_in,clock,reset);
input clock,reset;
output data_in;
reg data_in;
reg [63:0]data0,data1,data2;
integer i,j,k;
always @(posedge clock)
if(reset==1)
begin
i=63;
j=63;
k=63;
data0=64'b 110010100110111110011100011110000011111100001110;
data1=64'b 100010100110111110011100011110000011111100001110; //63rd bit
data2=64'b 110010100110011110011100011110000011111100001110; //52 bit
end
else if(reset==0)
begin
data_in=data0;
i=i-1;
if(i==-1)
begin
data_in= data1[j];
j=j-1;
end
if(i==-1 & j==-1)
begin
data_in=data2[k];
k=k-1;
end
end
endmodule
data0,data1.data2 are the three values which i want to give to the data_in ,I designed this code ucf file as well but defined only reset and clock signals and left data_in signal is this data_in signal connected with the input data_in in my verilog file ,i aded the bits files of my verilog code and this file,s bit file and the mcs file to the prom but when i ran the code no output appeared on leds