[SOLVED] Code for asymmetric mosfet with LDD only at the source side.

[Kimaya]

Silvaco Code for asymmetric mosfet with LDD only at the source side.

Hi,
Can anyone please tell me what is the silvaco code or program flow if i want to go for an asymmetric MOSFET with LDD at the source side only. I tried my level best to make the changes in mos1ex01 code so that i could remove the LDD from drain side and have it only at the source side but all my efforts were in vain. Please help me, i will be obliged.

 

[Kenneth_Potter]

A simple way would be to create LDD oxide over the polysilison at both the Source and Drain Side. Then simply use the etch right command selecting Oxide (assuming you use an oxide LDD spacer) and give it the co-ordinate you want to start etching at.

Then perform your source drain implants. You will now have an LDD at the source but nothing at the drain. No doubt there are other solutions but this is very simple and fast.

 

[Kimaya]

Hello sir, thank you so much for your valuable suggestion. I could implement the asymmetric MOSFET successfully.
Can you please further guide me if i want to scale down the gate length to 40 nm, what would be the probable change that i must make in mos1ex01 code?

 

[Kenneth_Potter]

Hi Kimaya

I dont have the code to hand but there are excellent examples in the Silvaco examples section. There is an explicit example on how to alter the code so you can have a variable gate length which you can change the variable accordingly to scale your gate length. Since its in the examples I will let you do the search.

 

[Kimaya]

Thanks for the reply, i will do that.

 

[Kimaya]

Hello, can you please tell me what would be the code to have a 2nm gate oxide thickness, i mean i don't know what values of diff time and temp are to be taken to achieve Tox=2nm. Thank you.

 

[Kenneth_Potter]

Hi

You would undertake a diffusion step with oxygen (dry) as the wet oxide would grow far too quickly to achieve such a thin gate oxide.

You as the designer will choose the temperature. In actual processing 1000C is usually taken to create a high quality gate oxide, but as the temperature increases so does the growth rate so that temperature may be too high.

Once you have set the temperature you need to choose a value of time in minutes, for such a thin gate oxide I would recommend starting at around 5 minutes.
Once the diffusion step is complete use the extraction tools to extract the gate oxide thickness. If its too thin < 2nm then increase the diffusion time until you reach an optimum of 2nm +/- 10%

Best wishes Ken.

 

[Kimaya]

Hi thank you it really helped me.

Can you please tell me if i create (asymmetric) MOS structure with drain diffusion depth (Xj drain) deeper than source diffusion depth (Xj source) then what would be its advantage over the corresponding symmetric structure.

Because i had actually simulated these structures both symmetric and asymmetric and found that Ion asym > Ion symm
but Ioff in asymmetric was also greater than the symmetric one.

What do you think how is this asymmetric structure advantageous over symmetric where Xj at both source and drain is same?

Thank you.