Code for 8_bit counter with borrow, not getting simulation

[ansaraet]

I have written this code for 8_bit counter with borrow but i am not getting simulation in xilinx. actually what i want is borrow bit which can be given to one o/p of a NAND gate....Can one help me with this code. Code attached...
Thanks



--Inverter --component #1
library ieee;
use ieee.std_logic_1164.all;

entity INVERTER is
port( A1:in std_logic;
C1: out std_logic
);
attribute pin_assign : string; --Pin assign
attribute pin_assign of A1 : signal is "5";

end INVERTER;
architecture behv of Inverter is
begin
C1 <= (NOT A1) after 15 ns ; --behavior Inver

end behv;

--------------------------------------------------------------
--nand gate1 --component #2
library ieee;
use ieee.std_logic_1164.all;

entity NAND_GATE1 is
port( A2: in std_logic;
B2: in std_logic;
C2: out std_logic
);
attribute pin_assign : string; --Pin assign
attribute pin_assign of A2 : signal is "7";
attribute pin_assign of B2 : signal is "8";
attribute pin_assign of C2 : signal is "9";
end NAND_GATE1;

architecture behv of NAND_GATE1 is
begin
process(A2,B2)
begin
C2 <= (A2 nand B2) after 15 ns; --behavior Nand
end process;
end behv;
---------------------------------------------------
--nand gate 2 --component #3
library ieee;
use ieee.std_logic_1164.all;

entity NAND_GATE2 is
port( A3:in std_logic;
B3:in std_logic;
C3ut std_logic
);
attribute pin_assign : string; --Pin assign
attribute pin_assign of A3 : signal is "10";
attribute pin_assign of B3 : signal is "11";
attribute pin_assign of C3 : signal is "12";
end NAND_GATE2;
architecture behv of NAND_GATE2 is
begin
process(A3,B3)
begin
C3 <= (A3 nand B3) after 15 ns; -- behavior Nand
end process;
end behv;
------------------------------------------------------------------
--nand gate 3 --component #4
library ieee;
use ieee.std_logic_1164.all;

entity NAND_GATE3 is
port( A4:in std_logic;
B4:in std_logic; --We can assign pin #'s--
C4ut std_logic
);
attribute pin_assign : string; --Pin assign
attribute pin_assign of A4 : signal is "13";
attribute pin_assign of B4 : signal is "14";
attribute pin_assign of C4 : signal is "15";
end NAND_GATE3;
architecture behv of NAND_GATE3 is
begin
process(A4,B4)
begin
C4 <= (A4 nand B4) after 15 ns; -- behavior Nand
end process;
end behv;
------------------------------------------------------------------------

--counter1 --component #7
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity UD_COUNTER1 is
port ( Clk,CLEAR,UP,DOWN : in std_logic;
--Carry : out std_logic;
Borrow : out std_logic;
DIN : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0));
attribute pin_assign : string; -- Pin assign
--attribute pin_assign of CLK : signal is "22";
attribute pin_assign of CLEAR : signal is "23";
--attribute pin_assign of LOAD : signal is "24";
--attribute pin_assign of Carry : signal is "25";
attribute pin_assign of Borrow : signal is "26";
attribute pin_assign of UP : signal is "27";
attribute pin_assign of DOWN : signal is "28";
attribute pin_assign of DIN : signal is "29,30,31,32,33,34,35,36";
attribute pin_assign of Q : signal is "37,38,39,40,41,42,43,44";
end UD_COUNTER1;
architecture behvv of UD_COUNTER1 is
signal Q_IN : std_logic_vector(7 downto 0); -- Internal counter signal
begin
-- behavior describe the counter
Q <= Q_IN; -- Set output
process( Clk,CLEAR,UP,DOWN ) begin
if CLEAR='1' then -- CLEAR = ON ?
Q_IN <= "00000000"; -- Yes. Counter clear
elsif CLK='1' and CLK'event then -- Clock in ?
-- Set Input to Output
if UP='1' then -- Yes. Up count ?
Q_IN <= Q_IN + '1';
if DOWN= '1' then
Q_IN <= Q_IN - '1'; ------Yes. Down Count?
else



if Q_IN<= "00000000" then
Borrow <= '0';
if Q_IN <="11111111" then
Q_IN <= DIN;


end if;
end if;
end if;
end if;
end if;



end process;
end architecture;


---------------------------------------------------------------------------------
library ieee; --top level circuit
use ieee.std_logic_1164.all;
use work.all;

entity comb_ckt is
port( A1: in std_logic;
A2: in std_logic;
B2:in std_logic;
A3:in std_logic;
B3:in std_logic;
A4:in std_logic;
B4:in std_logic;

C1ut std_logic;
C2ut std_logic;
C3ut std_logic;
C4ut std_logic;

CLK,CLEAR,UP,DOWN: in std_logic;
DIN : in std_logic_vector(7 downto 0);

Borrow : out std_logic;
Q : out std_logic_vector(7 downto 0));

end comb_ckt;

architecture struct of comb_ckt is

component Inverter is -- as entity of NAND_GATE1
port( A1: in std_logic;

C1: out std_logic
);
end component;
component NAND_GATE1 is -- as entity of NAND_GATE2
port( A2: in std_logic;
B2: in std_logic;
C2: out std_logic
);
end component;
component NAND_GATE2 is -- as entity of NAND_GATE2
port( A3: in std_logic;
B3: in std_logic;
C3: out std_logic
);
end component;

component NAND_GATE3 is -- as entity of NAND_GATE2
port( A4: in std_logic;
B4: in std_logic;
C4: out std_logic
);
end component;


component UD_COUNTER1 is -- as entity of ud_counter1
port ( CLK,CLEAR,UP,DOWN : in std_logic;
DIN : in std_logic_vector(7 downto 0);

Borrow : out std_logic;
Q : out std_logic_vector(7 downto 0));
end component;

signal A: std_logic; ------Inverter out
signal B: std_logic; -------Nand gate 1 out
signal C: std_logic; -------Nand gate 2 out
signal D: std_logic; -------or gate2 in
signal E: std_logic; --- signal just like wire ---or gate2 in
signal F: std_logic; -------or gate 2 out
signal G: std_logic; -------Nand gate3 out
signal H: std_logic;
--signal I: std_logic;
signal J: std_logic;
----Signal K: std_logic;
begin

---use sign "=>" to clarify the pin mapping

Gate1: Inverter port map (A1=>A1,C1=>A); ---Ok
---------------------------------------------------------
Gate2: NAND_GATE1 port map(A2=>A, B2=>Clk, C2=>B); ---Ok
Gate3: NAND_GATE2 port map(A3=>B2, B3=>A1, C3=>C);
-----------------------------------------------------------
---Ok

Gate5: NAND_GATE3 port map(A4=>A4, B4=>D, C4=>G);


------------------------------------------------------------
Gate7: UD_Counter1 port map (Clk=>Clk,DIN=>DIN,CLEAR=>G,UP=>B,DOWN=>C,Borrow=>D,Q=>Q);

end struct;

---------------------------------------------------------------------------------------