In addition to random mismatch between transistors, there may be a systematic mismatch caused by the layout - like difference in power/ground nets resistance and IR voltage drop for the two (or for many) transistors, difference in resistance and/or delay on other nets connected to them, difference in device instance parameters caused by layout (such as well proximity effect, stress effect, etc.) - these also need to be analyzed and verified (especially in advanced nodes with high parasitics).
Max