CMOS Combinational/seqential Logic Circuits

[tomorrowglue]

what is rise time in logic circuits

Hi,

When designing CMOS circuits for stand cell library, why symmetric rise/fall transition time is important? Is balanced rise/fall propagation delay of a single arc also required, and why? For multiple inputs circuits, do the propagation delays of different arcs need to be balanced, and why?

Things I can think of to consider when designing CMOS circuits are:
1) power
2) timing constraints: allowable propogation delay and rise/fall slew

Any other things?

Thank you.

 

[kumar_eee]

what is clock in logic circuits

When you want to reduce the delay that present in the clock path, you should have the equal rise & fall time buffer. So that there wont be any change in clock path, otherwise you might end up in timing violations..

 

[tomorrowglue]

Thank you kumar_eee. Equal rise/fall on clock path is for 50% duty cycle is that right? Is there a spectial group of cells that are for clock path specificly? My question is for those cells (if any) that will never be used on clock path, do they need to have equal rise/fall time? Can regular AND OR gates be on clock path?

 

[kumar_eee]

Equal rise/fall time means not 50% duty cycle. duty cycle means the clock pulse duration of High & Low.

Its not necessary that all cells have equal rise & fall time. Again, it depends on the library requirements. When you design the library cells with equal rise/fall time, it requires more effort.

Normally we use buffers/inverters(with equal rise & fall time) in clock path. We dont use any other combinational cells in clock path. The only cell apart from inverters/buffers we use in clock path is clock gate cell.

 

[tomorrowglue]

kumar_eee, could you explain in your first reply "So that there wont be any change in clock path, otherwise you might end up in timing violations". I guess you talked equal rise/fall edge of clock is important - why it is important? Could you give an example?