[SOLVED] CMOS Challenge: What is this?

[papanatas]

Dear forum members,

I've been working for a while in the reverse engineering of an old IC, just a hobbyist project (im not an electical engineer).

There's one component in the circuit that I havent been able to figure out its function yet so i'm reaching out to you guys for help.

Below you will find two images of it, one full metal, the other one with almost no metal left, and my notes.

To me it looks like it takes an input signal and just drives it to Gnd through a blob of polysilicon, as you can also see Vdd does not connect and nwell avoids its surface. Could this be a pull resistor? I'm not an electrical engineering or anything similar and i'm quite lost when out of the digital logic domain.

Thanks for your help.

 

[dick_freebird]

Looks more like a poor-boy well-poly-metal capacitor,
like for local decoupling or peaking or frequency
compensation.

 

[papanatas]

Hi Dick, thanks for your input, that was a great tip. Just found **broken link removed** online showing a standard cell nmos decoupling capacitor. While the cell is almost identical, it puzzles me the fact that the poly on my cell does not cross the ndiff completely. Any thoughts on that?

Looks more like a poor-boy well-poly-metal capacitor,
like for local decoupling or peaking or frequency
compensation.

 

[dick_freebird]

Looks like the choice was to avoid line-on-line and put
the poly inside the well other than the contacts. There
could be design rules that dictated the construction, or
it could simply be "artist's discretion". In general to get
the best and most consistent breakdown you'd prefer
the plates to avoid as many steps as possible, or to
minimise the step cross-section (a not-like-the-rest
feature in what you'd like to be a uniform plate).