So, you need more than 63mS of transconductance and at least 10GHz of transit frequency in all mosfets to achieve 1GHz UGF with 45° phase margin (and it would be an upper limit). The 180nm process provide core devices with f_t ≈60GHz, you would like to use 3.3V so I/O mosfets, which probably has Lmin 500nm and f_t in order of 5GHz. Then, forget with any known single stage architecture. You could consider using a core devices with 3.3V, however they has to be ensured to safe operation (all SOA, reliability checks, etc).