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CML frequency divider - does the lower bound exist?

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sharkies

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CML frequency divider

I was working on a CML frequency divider, and realized that it doesn't work for low frequencies, 1GHZ and below, or 100MHz for example. It works when I pull up the frequency to 1GHz and above. Does a CML frequency divider have a lower frequency bound? cause this just sounds weird. Afterall, it is two D flips connected together.
I need a divider for roughtly 700MHz, any suggestions? perhaps TSPC will do the job?

thanks
 


Re: CML frequency divider

For 700MHz even the static CMOS flops would work in any technology better than 0.13u roughly.
There is no low frequency limit for CML as you have a latch, whereas TSPC is limited on the lower side.
Can you post the schematic and waveforms
 

CML frequency divider

I have built a static CMOS divider that runs reliably (delivered
multiple production lots, flight hardware) at over 1GHz in
0.5um FDSOI. Full MIL temp range too, with an ECL compatible
input and 4 quadrature output phases. More than this, I must
not say.

So CML ought to be fine. Perhaps you are seeing some
sort of blocking / coupling effect (too small a blocking
cap from the RF ports?) or maybe the risetime is too leisurely
and the gain too low, to make the flip flops clock reliably -
an indecision region? Perhaps you want to gain it up with a
few inverter stages so you get it to limit into "true digital"
operation?
 

I am having the same problem. the CML divider seem to work fine in the Giga-hertz region while at lower frequencies in MHz it doesn't work.
I am working on 0.13u tech. i have made an ac analysis and it gives me weird results
Plz anyone can help.
Thx in advance
 

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